PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written.
Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
---
target/ppc/cpu.h | 3 +++
target/ppc/cpu_init.c | 2 +-
target/ppc/power8_pmu.c | 27 ++++++++++++++++++++-------
target/ppc/spr_tcg.h | 1 +
target/ppc/translate.c | 12 ++++++++++++
5 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4d4886ac74..76b462c3c8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,6 +363,9 @@ typedef struct ppc_v3_pate_t {
#define MMCR1_PMC4SEL_START 56
#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
+/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
+#define CTRL_RUN PPC_BIT(63)
+
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 07c79745ba..0013cba5ff 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6748,7 +6748,7 @@ static void register_book3s_ctrl_sprs(CPUPPCState *env)
{
spr_register(env, SPR_CTRL, "SPR_CTRL",
SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
+ SPR_NOACCESS, &spr_write_CTRL,
0x00000000);
spr_register(env, SPR_UCTRL, "SPR_UCTRL",
&spr_read_ureg, SPR_NOACCESS,
diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c
index 9769c0ff35..f584480fde 100644
--- a/target/ppc/power8_pmu.c
+++ b/target/ppc/power8_pmu.c
@@ -133,17 +133,15 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong
value)
}
}
-static bool pmc_counting_insns(CPUPPCState *env, int sprn)
+static bool pmc_counting_insns(CPUPPCState *env, int sprn,
+ uint8_t event)
{
bool ret = false;
- uint8_t event;
if (sprn == SPR_POWER_PMC5) {
return true;
}
- event = get_PMC_event(env, sprn);
-
/*
* Event 0x2 is an implementation-dependent event that IBM
* POWER chips implement (at least since POWER8) that is
@@ -158,8 +156,15 @@ static bool pmc_counting_insns(CPUPPCState *env, int sprn)
return event == 0x2 || event == 0xFE;
case SPR_POWER_PMC2:
case SPR_POWER_PMC3:
- case SPR_POWER_PMC4:
return event == 0x2;
+ case SPR_POWER_PMC4:
+ /*
+ * Event 0xFA is the "instructions completed with run latch
+ * set" event. Consider it as instruction counting event.
+ * The caller is responsible for handling it separately
+ * from PM_INST_CMPL.
+ */
+ return event == 0x2 || event == 0xFA;
default:
break;
}
@@ -173,8 +178,16 @@ void helper_insns_inc(CPUPPCState *env, uint32_t num_insns)
int sprn;
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
- if (pmc_counting_insns(env, sprn)) {
- env->spr[sprn] += num_insns;
+ uint8_t event = get_PMC_event(env, sprn);
+
+ if (pmc_counting_insns(env, sprn, event)) {
+ if (sprn == SPR_POWER_PMC4 && event == 0xFA) {
+ if (env->spr[SPR_CTRL] & CTRL_RUN) {
+ env->spr[SPR_POWER_PMC4] += num_insns;
+ }
+ } else {
+ env->spr[sprn] += num_insns;
+ }
}
}
}
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 51fbc081de..5e6ed36eb1 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
+void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b7235a2be0..866b1d2b34 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -402,6 +402,18 @@ void spr_write_generic(DisasContext *ctx, int sprn, int
gprn)
spr_store_dump_spr(sprn);
}
+void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
+{
+ spr_write_generic(ctx, sprn, gprn);
+
+ /*
+ * Write in SPR_CTRL must force a new translation block,
+ * allowing the PMU to calculate the run latch events with
+ * more accuracy.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+}
+
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
{
--
2.31.1
