On Mon, Aug 30, 2021 at 3:51 AM Alexey Baturo <baturo.ale...@gmail.com> wrote:
>
> Signed-off-by: Alexey Baturo <space.monkey.deliv...@gmail.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 96 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 96 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 7330ff5a19..140178d23c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -334,6 +334,38 @@
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
>
> +/*
> + * User PointerMasking registers
> + * NB: actual CSR numbers might be changed in future
> + */
> +#define CSR_UMTE 0x4c0
> +#define CSR_UPMMASK 0x4c1
> +#define CSR_UPMBASE 0x4c2
> +
> +/*
> + * Machine PointerMasking registers
> + * NB: actual CSR numbers might be changed in future
> + */
> +#define CSR_MMTE 0x3c0
> +#define CSR_MPMMASK 0x3c1
> +#define CSR_MPMBASE 0x3c2
> +
> +/*
> + * Supervisor PointerMaster registers
> + * NB: actual CSR numbers might be changed in future
> + */
> +#define CSR_SMTE 0x1c0
> +#define CSR_SPMMASK 0x1c1
> +#define CSR_SPMBASE 0x1c2
> +
> +/*
> + * Hypervisor PointerMaster registers
> + * NB: actual CSR numbers might be changed in future
> + */
> +#define CSR_VSMTE 0x2c0
> +#define CSR_VSPMMASK 0x2c1
> +#define CSR_VSPMBASE 0x2c2
> +
> /* mstatus CSR bits */
> #define MSTATUS_UIE 0x00000001
> #define MSTATUS_SIE 0x00000002
> @@ -531,4 +563,68 @@ typedef enum RISCVException {
> #define MIE_UTIE (1 << IRQ_U_TIMER)
> #define MIE_SSIE (1 << IRQ_S_SOFT)
> #define MIE_USIE (1 << IRQ_U_SOFT)
> +
> +/* General PointerMasking CSR bits*/
> +#define PM_ENABLE 0x00000001ULL
> +#define PM_CURRENT 0x00000002ULL
> +#define PM_INSN 0x00000004ULL
> +#define PM_XS_MASK 0x00000003ULL
> +
> +/* PointerMasking XS bits values */
> +#define PM_EXT_DISABLE 0x00000000ULL
> +#define PM_EXT_INITIAL 0x00000001ULL
> +#define PM_EXT_CLEAN 0x00000002ULL
> +#define PM_EXT_DIRTY 0x00000003ULL
> +
> +/* Offsets for every pair of control bits per each priv level */
> +#define XS_OFFSET 0ULL
> +#define U_OFFSET 2ULL
> +#define S_OFFSET 5ULL
> +#define M_OFFSET 8ULL
> +
> +#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
> +#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
> +#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
> +#define U_PM_INSN (PM_INSN << U_OFFSET)
> +#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
> +#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
> +#define S_PM_INSN (PM_INSN << S_OFFSET)
> +#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
> +#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
> +#define M_PM_INSN (PM_INSN << M_OFFSET)
> +
> +/* mmte CSR bits */
> +#define MMTE_PM_XS_BITS PM_XS_BITS
> +#define MMTE_U_PM_ENABLE U_PM_ENABLE
> +#define MMTE_U_PM_CURRENT U_PM_CURRENT
> +#define MMTE_U_PM_INSN U_PM_INSN
> +#define MMTE_S_PM_ENABLE S_PM_ENABLE
> +#define MMTE_S_PM_CURRENT S_PM_CURRENT
> +#define MMTE_S_PM_INSN S_PM_INSN
> +#define MMTE_M_PM_ENABLE M_PM_ENABLE
> +#define MMTE_M_PM_CURRENT M_PM_CURRENT
> +#define MMTE_M_PM_INSN M_PM_INSN
> +#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN
> | \
> + MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN
> | \
> + MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN
> | \
> + MMTE_PM_XS_BITS)
> +
> +/* (v)smte CSR bits */
> +#define SMTE_PM_XS_BITS PM_XS_BITS
> +#define SMTE_U_PM_ENABLE U_PM_ENABLE
> +#define SMTE_U_PM_CURRENT U_PM_CURRENT
> +#define SMTE_U_PM_INSN U_PM_INSN
> +#define SMTE_S_PM_ENABLE S_PM_ENABLE
> +#define SMTE_S_PM_CURRENT S_PM_CURRENT
> +#define SMTE_S_PM_INSN S_PM_INSN
> +#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN
> | \
> + SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN
> | \
> + SMTE_PM_XS_BITS)
> +
> +/* umte CSR bits */
> +#define UMTE_U_PM_ENABLE U_PM_ENABLE
> +#define UMTE_U_PM_CURRENT U_PM_CURRENT
> +#define UMTE_U_PM_INSN U_PM_INSN
> +#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
> +
> #endif
> --
> 2.20.1
>
>
