All variations of shifts on 64-bit values are available in the 128-bit ISA, so we add them now.
Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org> --- target/riscv/insn32.decode | 10 +++++ target/riscv/translate.c | 4 +- target/riscv/insn_trans/trans_rvi.c.inc | 58 +++++++++++++++++++++++++ 3 files changed, 70 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index eea540cea9..be8d6aa85f 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -22,6 +22,7 @@ %rs1 15:5 %rd 7:5 %sh5 20:5 +%sh6 20:6 %sh7 20:7 %csr 20:12 @@ -92,6 +93,9 @@ # Formats 64: @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd +# Formats 128: +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd + # *** Privileged Instructions *** ecall 000000000000 00000 000 00000 1110011 ebreak 000000000001 00000 000 00000 1110011 @@ -168,8 +172,14 @@ ldu ............ ..... 111 ..... 0000011 @i lq ............ ..... 010 ..... 0001111 @i sq ............ ..... 100 ..... 0100011 @s addid ............ ..... 000 ..... 1011011 @i +sllid 000000 ...... ..... 001 ..... 1011011 @sh6 +srlid 000000 ...... ..... 101 ..... 1011011 @sh6 +sraid 010000 ...... ..... 101 ..... 1011011 @sh6 addd 0000000 ..... ..... 000 ..... 1111011 @r subd 0100000 ..... ..... 000 ..... 1111011 @r +slld 0000000 ..... ..... 001 ..... 1111011 @r +srld 0000000 ..... ..... 101 ..... 1111011 @r +srad 0100000 ..... ..... 101 ..... 1111011 @r # *** RV32M Standard Extension *** mul 0000001 ..... ..... 000 ..... 0110011 @r diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 120841de48..195dc3f461 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -624,8 +624,8 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, gen_set_gpr(ctx, a->rd, dest); } else if (is_128bit(ctx)) { - if ((ctx->w && a->shamt >= 32) - || (!ctx->w && a->shamt >= 128)) { + if ((ctx->w && a->shamt >= 32) || (ctx->d && a->shamt >= 64) + || (!ctx->w && !ctx->d && a->shamt >= 128)) { return false; } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 05e13bbc1d..1a1defb102 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -888,6 +888,39 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) NULL, gen_sraiw_tl, gen_sraiw_i128); } +static bool trans_sllid(DisasContext *ctx, arg_sllid *a) +{ + REQUIRE_128BIT(ctx); + ctx->d = true; + return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_slliwd_i128); +} + +static void gen_srlid_i128(TCGv retl, TCGv reth, + TCGv srcl, TCGv srch, target_long shamt) +{ + tcg_gen_shri_tl(retl, srcl, shamt); +} + +static bool trans_srlid(DisasContext *ctx, arg_srlid *a) +{ + REQUIRE_128BIT(ctx); + ctx->d = true; + return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_srlid_i128); +} + +static void gen_sraid_i128(TCGv retl, TCGv reth, + TCGv srcl, TCGv srch, target_long shamt) +{ + tcg_gen_sari_tl(retl, srcl, shamt); +} + +static bool trans_sraid(DisasContext *ctx, arg_sraid *a) +{ + REQUIRE_128BIT(ctx); + ctx->d = true; + return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_sraid_i128); +} + static void gen_addw_i128(TCGv retl, TCGv reth, TCGv src1l, TCGv src1h, TCGv src2l, TCGv src2h) @@ -960,6 +993,31 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) NULL, tcg_gen_sar_tl, gen_srawd_i128); } +/* Translation functions for 64-bit operations specific to RV128 */ +static bool trans_slld(DisasContext *ctx, arg_slld *a) +{ + REQUIRE_128BIT(ctx); + ctx->d = true; + return gen_shift(ctx, a, EXT_NONE, + tcg_gen_shl_tl, tcg_gen_shl_tl, gen_sllwd_i128); +} + +static bool trans_srld(DisasContext *ctx, arg_srld *a) +{ + REQUIRE_128BIT(ctx); + ctx->d = true; + return gen_shift(ctx, a, EXT_ZERO, + tcg_gen_shr_tl, tcg_gen_shr_tl, gen_srlwd_i128); +} + +static bool trans_srad(DisasContext *ctx, arg_srad *a) +{ + REQUIRE_128BIT(ctx); + ctx->d = true; + return gen_shift(ctx, a, EXT_SIGN, + tcg_gen_sar_tl, tcg_gen_sar_tl, gen_srawd_i128); +} + static bool trans_fence(DisasContext *ctx, arg_fence *a) { /* FENCE is a full memory barrier. */ -- 2.33.0