Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration

[LIU Zhiwei]

On 2021/10/8 上午1:47, Richard Henderson wrote:

Move the MXL_RV* defines to enumerators.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>

Reviewed-by: LIU Zhiwei<zhiwei_...@c-sky.com>

Zhiwei

---
  target/riscv/cpu_bits.h | 8 +++++---
  1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..e248c6bf6d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -364,9 +364,11 @@
  #define MISA32_MXL          0xC0000000
  #define MISA64_MXL          0xC000000000000000ULL

-#define MXL_RV32 1

-#define MXL_RV64            2
-#define MXL_RV128           3
+typedef enum {
+    MXL_RV32  = 1,
+    MXL_RV64  = 2,
+    MXL_RV128 = 3,
+} RISCVMXL;

/* sstatus CSR bits */

  #define SSTATUS_UIE         0x00000001