This patch add the irq hierarchy for the virt board. Signed-off-by: Xiaojuan Yang <yangxiaoj...@loongson.cn> Signed-off-by: Song Gao <gaos...@loongson.cn> --- hw/loongarch/ls3a5000_virt.c | 49 ++++++++++++++++++++++++++++++++++++ include/hw/pci-host/ls7a.h | 4 +++ 2 files changed, 53 insertions(+)
diff --git a/hw/loongarch/ls3a5000_virt.c b/hw/loongarch/ls3a5000_virt.c index 115954033e..89fee1fd9b 100644 --- a/hw/loongarch/ls3a5000_virt.c +++ b/hw/loongarch/ls3a5000_virt.c @@ -16,6 +16,9 @@ #include "sysemu/runstate.h" #include "sysemu/reset.h" #include "hw/loongarch/loongarch.h" +#include "hw/intc/loongarch_extioi.h" +#include "hw/intc/loongarch_pch_pic.h" +#include "hw/intc/loongarch_pch_msi.h" #include "hw/pci-host/ls7a.h" CPULoongArchState *cpu_states[LOONGARCH_MAX_VCPUS]; @@ -103,6 +106,49 @@ static const MemoryRegionOps loongarch_qemu_ops = { }, }; +static void ls3a5000_irq_init(MachineState *machine, CPULoongArchState *env[]) +{ + LoongarchMachineState *lsms = LOONGARCH_MACHINE(machine); + DeviceState *extioi, *pch_pic, *pch_msi; + SysBusDevice *d; + int cpu, pin, i; + + extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); + d = SYS_BUS_DEVICE(extioi); + sysbus_realize_and_unref(d, &error_fatal); + sysbus_mmio_map(d, 0, APIC_BASE); + + for (i = 0; i < EXTIOI_IRQS; i++) { + sysbus_connect_irq(d, i, qdev_get_gpio_in(extioi, i)); + } + + for (cpu = 0; cpu < machine->smp.cpus; cpu++) { + /* cpu_pin[9:2] <= intc_pin[7:0] */ + for (pin = 0; pin < LS3A_INTC_IP; pin++) { + sysbus_connect_irq(d, (EXTIOI_IRQS + cpu * 8 + pin), + env[cpu]->irq[pin + 2]); + } + } + + pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); + d = SYS_BUS_DEVICE(pch_pic); + sysbus_realize_and_unref(d, &error_fatal); + sysbus_mmio_map(d, 0, LS7A_IOAPIC_REG_BASE); + + for (int i = 0; i < 32; i++) { + sysbus_connect_irq(d, i, lsms->pch_irq[i]); + } + + pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); + d = SYS_BUS_DEVICE(pch_msi); + sysbus_realize_and_unref(d, &error_fatal); + sysbus_mmio_map(d, 0, LS7A_PCH_MSI_ADDR_LOW); + for (i = 0; i < 224; i++) { + sysbus_connect_irq(d, i, lsms->pch_irq[i + 32]); + } + +} + static void ls3a5000_virt_init(MachineState *machine) { const char *cpu_model = machine->cpu_type; @@ -175,6 +221,9 @@ static void ls3a5000_virt_init(MachineState *machine) memory_region_add_subregion(address_space_mem, PM_MMIO_ADDR, iomem); + /*Initialize the IO interrupt subsystem*/ + ls3a5000_irq_init(machine, cpu_states); + LOONGARCH_SIMPLE_MMIO_OPS(FEATURE_REG, "loongarch_feature", 0x8); LOONGARCH_SIMPLE_MMIO_OPS(VENDOR_REG, "loongarch_vendor", 0x8); LOONGARCH_SIMPLE_MMIO_OPS(CPUNAME_REG, "loongarch_cpuname", 0x8); diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h index 4c95a11ab8..e957c8c855 100644 --- a/include/hw/pci-host/ls7a.h +++ b/include/hw/pci-host/ls7a.h @@ -24,6 +24,10 @@ #define LS7A_PCI_IO_BASE 0x18000000UL #define LS7A_PCI_IO_SIZE 0x00010000 +#define LS7A_PCH_REG_BASE 0x10000000UL +#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE) +#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL + typedef struct LS7APCIState LS7APCIState; typedef struct LS7APCIEHost { PCIExpressHost parent_obj; -- 2.27.0