From: Matheus Ferst <matheus.fe...@eldorado.org.br>
Signed-off-by: Luis Pires <luis.pi...@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate/vmx-impl.c.inc | 36 +++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 65075f0d03..6ce06b231d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -334,3 +334,5 @@ DSCRIQ 111111 ..... ..... ...... 001100010 .
@Z22_tap_sh_rc
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
+VCLZDM 000100 ..... ..... ..... 11110000100 @VX
+VCTZDM 000100 ..... ..... ..... 11111000100 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index f0f6d561e1..ee9426862c 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1577,6 +1577,42 @@ static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
+{
+ static const TCGOpcode vecop_list[] = { 0 };
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_CNTLZDM,
+ .opt_opc = vecop_list,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
+static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
+{
+ static const TCGOpcode vecop_list[] = { 0 };
+ static const GVecGen3 g = {
+ .fni8 = gen_helper_CNTTZDM,
+ .opt_opc = vecop_list,
+ .vece = MO_64,
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &g);
+
+ return true;
+}
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.25.1
