On 1 November 2011 22:31, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 28 October 2011 18:40, Rabin Vincent <ra...@rab.in> wrote: >> The first enable set/clear register (which controls the PPIs and SGIs) >> is supposed to be banked for each processor. Currently it is just >> handled globally and this prevents recent SMP Linux kernels from >> booting, because CPU0 stops receiving localtimer interrupts when CPU1 >> disables them locally.
> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> This has just missed the 1.0rc0 deadline but as it's a bug fix we can put it into rc1. -- PMM
