This adds initial support for the native debug via the Trigger Module, as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now, which is mainly used for hardware breakpoint and watchpoint. The number of type 2 triggers implemented is 2, which is the number that we can find in the SiFive U54/U74 cores. [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf Bin Meng (5): target/riscv: Add initial support for native debug target/riscv: debug: Implement debug related TCGCPUOps target/riscv: Add a config option for native debug target/riscv: csr: Hook debug CSR read/write hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() include/hw/core/tcg-cpu-ops.h | 1 + target/riscv/cpu.h | 7 + target/riscv/debug.h | 114 +++++++++ target/riscv/cpu.c | 14 ++ target/riscv/csr.c | 57 +++++ target/riscv/debug.c | 439 ++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 1 + 7 files changed, 633 insertions(+) create mode 100644 target/riscv/debug.h create mode 100644 target/riscv/debug.c -- 2.25.1
