On Fri, Jan 7, 2022 at 10:18 AM Atish Patra <ati...@rivosinc.com> wrote: > > The RISC-V privilege specification provides flexibility to implement > any number of counters from 29 programmable counters. However, the QEMU > implements all the counters. > > Make it configurable through pmu config parameter which now will indicate > how many programmable counters should be implemented by the cpu. > > Signed-off-by: Atish Patra <atish.pa...@wdc.com> > Signed-off-by: Atish Patra <ati...@rivosinc.com> > --- > target/riscv/cpu.c | 2 +- > target/riscv/cpu.h | 2 +- > target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++---------------- > 3 files changed, 65 insertions(+), 35 deletions(-) >
Reviewed-by: Bin Meng <bmeng...@gmail.com>
