On 7/1/22 01:48, Atish Patra wrote:
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Signed-off-by: Atish Patra <atish.pa...@wdc.com>
Signed-off-by: Atish Patra <ati...@rivosinc.com>
---
hw/riscv/virt.c | 38 ++++++++++++++++++++++++++++++++++++++
target/riscv/pmu.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
target/riscv/pmu.h | 1 +
3 files changed, 84 insertions(+)
+static void create_fdt_socket_pmu(RISCVVirtState *s,
+ int socket, uint32_t *phandle,
+ uint32_t *intc_phandles)
+{
+ int cpu;
+ char *pmu_name;
+ uint32_t *pmu_cells;
+ MachineState *mc = MACHINE(s);
+ RISCVCPU hart = s->soc[socket].harts[0];
+
+ pmu_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ pmu_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ pmu_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_PMU_OVF);
+ }
+
+ pmu_name = g_strdup_printf("/soc/pmu");
+ qemu_fdt_add_subnode(mc->fdt, pmu_name);
+ qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu");
+ riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name);
pmu_cells[] is not consumed...
+
+ g_free(pmu_name);
+ g_free(pmu_cells);
+}