From: Alistair Francis <alistair.fran...@wdc.com> Let's enable the Hypervisor extension by default. This doesn't affect named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Anup Patel <anup.pa...@wdc.com> Reviewed-by: Bin Meng <bmeng...@gmail.com> Message-Id: <20220105213937.1113508-7-alistair.fran...@opensource.wdc.com> --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9ea67bedd3..29749e834f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -627,7 +627,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), -- 2.31.1