From: Alistair Francis <alistair.fran...@wdc.com> This series adds a MO_ op to specify that a load instruction should produce a store fault. This is used on RISC-V to produce a store/amo fault when an atomic access fails.
This fixes: https://gitlab.com/qemu-project/qemu/-/issues/594 Alistair Francis (2): accel: tcg: Allow forcing a store fault on read ops targett/riscv: rva: Correctly generate a store/amo fault include/exec/memop.h | 2 + accel/tcg/cputlb.c | 11 ++++- target/riscv/insn_trans/trans_rva.c.inc | 56 ++++++++++++++++--------- 3 files changed, 48 insertions(+), 21 deletions(-) -- 2.31.1
