BALATON Zoltan <bala...@eik.bme.hu> writes:
> On Thu, 3 Feb 2022, Fabiano Rosas wrote:
>> This code applies only to the 6xx CPUs, so we can remove the switch
>> statement.
>>
>> Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
>> ---
>> target/ppc/excp_helper.c | 31 +++++++++++--------------------
>> 1 file changed, 11 insertions(+), 20 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 538905c4dd..80168355bd 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -553,7 +553,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>> {
>> CPUState *cs = CPU(cpu);
>> CPUPPCState *env = &cpu->env;
>> - int excp_model = env->excp_model;
>> target_ulong msr, new_msr, vector;
>> int srr0, srr1;
>>
>> @@ -695,26 +694,18 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
>> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error
>> */
>> case POWERPC_EXCP_DLTLB: /* Data load TLB miss
>> */
>> case POWERPC_EXCP_DSTLB: /* Data store TLB miss
>> */
>> - switch (excp_model) {
>> - case POWERPC_EXCP_6xx:
>> - /* Swap temporary saved registers with GPRs */
>> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
>> - new_msr |= (target_ulong)1 << MSR_TGPR;
>> - hreg_swap_gpr_tgpr(env);
>> - }
>> - /* fall through */
>> - case POWERPC_EXCP_7x5:
>> - ppc_excp_debug_sw_tlb(env, excp);
>> -
>> - msr |= env->crf[0] << 28;
>> - msr |= env->error_code; /* key, D/I, S/L bits */
>> - /* Set way using a LRU mechanism */
>> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
>> - break;
>> - default:
>> - cpu_abort(cs, "Invalid TLB miss exception\n");
>> - break;
>> + /* Swap temporary saved registers with GPRs */
>> + if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
>> + new_msr |= (target_ulong)1 << MSR_TGPR;
>> + hreg_swap_gpr_tgpr(env);
>
> I get this one...
>
>> }
>> +
>> + ppc_excp_debug_sw_tlb(env, excp);
>> +
>> + msr |= env->crf[0] << 28;
>> + msr |= env->error_code; /* key, D/I, S/L bits */
>> + /* Set way using a LRU mechanism */
>> + msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
>
> ...but not why this can be moved out from case or if. Is POWERPC_EXCP_7x5
> the same as POWERPC_EXCP_6xx now?
There is a fallthrough in the original code after the first block. So
POWERPC_EXCP_6xx does the TGPR work and then falls through to the debug
print and SRR1 setting.
