On Thu, 10 Feb 2022 at 04:04, Richard Henderson <richard.hender...@linaro.org> wrote: > > Set this as the kernel would, to 48 bits, to keep the computation > of the address space correct for PAuth. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/arm/cpu.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 5a9c02a256..92f19f919a 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -206,10 +206,11 @@ static void arm_cpu_reset(DeviceState *dev) > aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); > } > /* > + * Enable 48-bit address space (TODO: take reserved_va into account). > * Enable TBI0 but not TBI1. > * Note that this must match useronly_clean_ptr. > */ > - env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); > + env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37);
I think the kernel defaults to 39 bits if it's built for 4K pages (probably the usual setup), but OTOH we've been effectively using 48 bits previously so not changing that seems the best option. Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
