On 14/02/2022 12:14, Alex Bennée wrote:
"Matheus K. Ferst" <matheus.fe...@eldorado.org.br> writes:
On 11/02/2022 13:03, Alex Bennée wrote:
This builds vectorised versions of sha512 to exercise the vector code:
- aarch64 (AdvSimd)
- i386 (SSE)
- s390x (MVX)
- ppc64 (vector)
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20220202191242.652607-5-alex.ben...@linaro.org>
---
v2
- use -msse4.1 -O3 instead of -pentium4 for i386 build
---
tests/tcg/multiarch/sha512.c | 2 +-
tests/tcg/aarch64/Makefile.target | 7 +++++++
tests/tcg/arm/Makefile.target | 8 ++++++++
tests/tcg/i386/Makefile.target | 6 ++++++
tests/tcg/ppc64le/Makefile.target | 5 ++++-
tests/tcg/s390x/Makefile.target | 9 +++++++++
tests/tcg/x86_64/Makefile.target | 7 +++++++
7 files changed, 42 insertions(+), 2 deletions(-)
<snip>
diff --git a/tests/tcg/ppc64le/Makefile.target
b/tests/tcg/ppc64le/Makefile.target
index 480ff0898d..4f1d03dfcf 100644
--- a/tests/tcg/ppc64le/Makefile.target
+++ b/tests/tcg/ppc64le/Makefile.target
@@ -5,10 +5,13 @@
VPATH += $(SRC_PATH)/tests/tcg/ppc64le
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER8_VECTOR),)
-PPC64LE_TESTS=bcdsub non_signalling_xscv
+PPC64LE_TESTS=bcdsub non_signalling_xscv sha512-vector
endif
$(PPC64LE_TESTS): CFLAGS += -mpower8-vector
Since this test does not target a specific instruction, maybe it
should use -mvsx/-maltivec to allow the compiler to use newer
instructions.
I wasn't sure which vector instructions are supported by the TCG front
ends so if the above flags won't trip up the TCG I can add them to the
cflags.
AFAICT, we should have all vector instruction until POWER9. POWER10 is
WIP, but current versions of GCC/Clang are not emitting any of the
missing instructions, even with -mcpu=power10
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
