On Fri, Feb 11, 2022 at 2:45 PM Weiwei Li <liwei...@iscas.ac.cn> wrote: > > -- update extension check REQUIRE_ZDINX_OR_D > -- update double float point register read/write > > Co-authored-by: ardxwe <ard...@gmail.com> > Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvd.c.inc | 285 +++++++++++++++++------- > target/riscv/translate.c | 52 +++++ > 2 files changed, 259 insertions(+), 78 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvd.c.inc > b/target/riscv/insn_trans/trans_rvd.c.inc > index 091ed3a8ad..1397c1ce1c 100644 > --- a/target/riscv/insn_trans/trans_rvd.c.inc > +++ b/target/riscv/insn_trans/trans_rvd.c.inc > @@ -18,6 +18,19 @@ > * this program. If not, see <http://www.gnu.org/licenses/>. > */ > > +#define REQUIRE_ZDINX_OR_D(ctx) do { \ > + if (!ctx->cfg_ptr->ext_zdinx) { \ > + REQUIRE_EXT(ctx, RVD); \ > + } \ > +} while (0) > + > +#define REQUIRE_EVEN(ctx, reg) do { \ > + if (ctx->cfg_ptr->ext_zdinx && (get_xl(ctx) == MXL_RV32) && \ > + ((reg) & 0x1)) { \ > + return false; \ > + } \ > +} while (0) > + > static bool trans_fld(DisasContext *ctx, arg_fld *a) > { > TCGv addr; > @@ -47,10 +60,17 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) > static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); > + > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > + TCGv_i64 src3 = get_fpr_d(ctx, a->rs3); > + > gen_set_rm(ctx, a->rm); > - gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], > - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); > + gen_helper_fmadd_d(dest, cpu_env, src1, src2, src3); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -58,10 +78,17 @@ static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d > *a) > static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); > + > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > + TCGv_i64 src3 = get_fpr_d(ctx, a->rs3); > + > gen_set_rm(ctx, a->rm); > - gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], > - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); > + gen_helper_fmsub_d(dest, cpu_env, src1, src2, src3); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -69,10 +96,17 @@ static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d > *a) > static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); > + > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > + TCGv_i64 src3 = get_fpr_d(ctx, a->rs3); > + > gen_set_rm(ctx, a->rm); > - gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], > - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); > + gen_helper_fnmsub_d(dest, cpu_env, src1, src2, src3); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -80,10 +114,17 @@ static bool trans_fnmsub_d(DisasContext *ctx, > arg_fnmsub_d *a) > static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); > + > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > + TCGv_i64 src3 = get_fpr_d(ctx, a->rs3); > + > gen_set_rm(ctx, a->rm); > - gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], > - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); > + gen_helper_fnmadd_d(dest, cpu_env, src1, src2, src3); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -91,12 +132,16 @@ static bool trans_fnmadd_d(DisasContext *ctx, > arg_fnmadd_d *a) > static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > > - gen_set_rm(ctx, a->rm); > - gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env, > - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > + gen_set_rm(ctx, a->rm); > + gen_helper_fadd_d(dest, cpu_env, src1, src2); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -104,12 +149,16 @@ static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d > *a) > static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > > - gen_set_rm(ctx, a->rm); > - gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env, > - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > + gen_set_rm(ctx, a->rm); > + gen_helper_fsub_d(dest, cpu_env, src1, src2); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -117,12 +166,16 @@ static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d > *a) > static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > > - gen_set_rm(ctx, a->rm); > - gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env, > - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > + gen_set_rm(ctx, a->rm); > + gen_helper_fmul_d(dest, cpu_env, src1, src2); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -130,12 +183,16 @@ static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d > *a) > static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > > - gen_set_rm(ctx, a->rm); > - gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env, > - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > + gen_set_rm(ctx, a->rm); > + gen_helper_fdiv_d(dest, cpu_env, src1, src2); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -143,23 +200,34 @@ static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d > *a) > static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1); > > - gen_set_rm(ctx, a->rm); > - gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > > + gen_set_rm(ctx, a->rm); > + gen_helper_fsqrt_d(dest, cpu_env, src1); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > > static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a) > { > + REQUIRE_FPU; > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > + > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > if (a->rs1 == a->rs2) { /* FMOV */ > - tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); > + dest = get_fpr_d(ctx, a->rs1); > } else { > - tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], > - cpu_fpr[a->rs1], 0, 63); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > + tcg_gen_deposit_i64(dest, src2, src1, 0, 63); > } > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -167,15 +235,22 @@ static bool trans_fsgnj_d(DisasContext *ctx, > arg_fsgnj_d *a) > static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > + > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + > if (a->rs1 == a->rs2) { /* FNEG */ > - tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN); > + tcg_gen_xori_i64(dest, src1, INT64_MIN); > } else { > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > TCGv_i64 t0 = tcg_temp_new_i64(); > - tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); > - tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63); > + tcg_gen_not_i64(t0, src2); > + tcg_gen_deposit_i64(dest, t0, src1, 0, 63); > tcg_temp_free_i64(t0); > } > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -183,15 +258,22 @@ static bool trans_fsgnjn_d(DisasContext *ctx, > arg_fsgnjn_d *a) > static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > + > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + > if (a->rs1 == a->rs2) { /* FABS */ > - tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN); > + tcg_gen_andi_i64(dest, src1, ~INT64_MIN); > } else { > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > TCGv_i64 t0 = tcg_temp_new_i64(); > - tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN); > - tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); > + tcg_gen_andi_i64(t0, src2, INT64_MIN); > + tcg_gen_xor_i64(dest, src1, t0); > tcg_temp_free_i64(t0); > } > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -199,11 +281,15 @@ static bool trans_fsgnjx_d(DisasContext *ctx, > arg_fsgnjx_d *a) > static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > > - gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env, > - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > + gen_helper_fmin_d(dest, cpu_env, src1, src2); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -211,11 +297,15 @@ static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d > *a) > static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); > > - gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env, > - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > + gen_helper_fmax_d(dest, cpu_env, src1, src2); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -223,11 +313,15 @@ static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d > *a) > static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1); > > - gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_s_d(dest, cpu_env, src1); > + gen_set_fpr_hs(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -235,11 +329,15 @@ static bool trans_fcvt_s_d(DisasContext *ctx, > arg_fcvt_s_d *a) > static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd); > > - gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > > + gen_set_rm(ctx, a->rm); > + gen_helper_fcvt_d_s(dest, cpu_env, src1); > + gen_set_fpr_d(ctx, a->rd, dest); > mark_fs_dirty(ctx); > return true; > } > @@ -247,11 +345,14 @@ static bool trans_fcvt_d_s(DisasContext *ctx, > arg_fcvt_d_s *a) > static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1 | a->rs2); > > TCGv dest = dest_gpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > - gen_helper_feq_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + gen_helper_feq_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -259,11 +360,14 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) > static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1 | a->rs2); > > TCGv dest = dest_gpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > - gen_helper_flt_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + gen_helper_flt_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -271,11 +375,14 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) > static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1 | a->rs2); > > TCGv dest = dest_gpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > + TCGv_i64 src2 = get_fpr_d(ctx, a->rs2); > > - gen_helper_fle_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); > + gen_helper_fle_d(dest, cpu_env, src1, src2); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -283,11 +390,13 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) > static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1); > > TCGv dest = dest_gpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > > - gen_helper_fclass_d(dest, cpu_fpr[a->rs1]); > + gen_helper_fclass_d(dest, src1); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -295,12 +404,14 @@ static bool trans_fclass_d(DisasContext *ctx, > arg_fclass_d *a) > static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1); > > TCGv dest = dest_gpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > > gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_w_d(dest, cpu_env, cpu_fpr[a->rs1]); > + gen_helper_fcvt_w_d(dest, cpu_env, src1); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -308,12 +419,14 @@ static bool trans_fcvt_w_d(DisasContext *ctx, > arg_fcvt_w_d *a) > static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1); > > TCGv dest = dest_gpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > > gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_wu_d(dest, cpu_env, cpu_fpr[a->rs1]); > + gen_helper_fcvt_wu_d(dest, cpu_env, src1); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -321,12 +434,15 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, > arg_fcvt_wu_d *a) > static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd); > > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN); > > gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, src); > + gen_helper_fcvt_d_w(dest, cpu_env, src); > + gen_set_fpr_d(ctx, a->rd, dest); > > mark_fs_dirty(ctx); > return true; > @@ -335,12 +451,15 @@ static bool trans_fcvt_d_w(DisasContext *ctx, > arg_fcvt_d_w *a) > static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a) > { > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd); > > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO); > > gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, src); > + gen_helper_fcvt_d_wu(dest, cpu_env, src); > + gen_set_fpr_d(ctx, a->rd, dest); > > mark_fs_dirty(ctx); > return true; > @@ -350,12 +469,14 @@ static bool trans_fcvt_l_d(DisasContext *ctx, > arg_fcvt_l_d *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1); > > TCGv dest = dest_gpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > > gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_l_d(dest, cpu_env, cpu_fpr[a->rs1]); > + gen_helper_fcvt_l_d(dest, cpu_env, src1); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -364,12 +485,14 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, > arg_fcvt_lu_d *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1); > > TCGv dest = dest_gpr(ctx, a->rd); > + TCGv_i64 src1 = get_fpr_d(ctx, a->rs1); > > gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_lu_d(dest, cpu_env, cpu_fpr[a->rs1]); > + gen_helper_fcvt_lu_d(dest, cpu_env, src1); > gen_set_gpr(ctx, a->rd, dest); > return true; > } > @@ -392,12 +515,15 @@ static bool trans_fcvt_d_l(DisasContext *ctx, > arg_fcvt_d_l *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd); > > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN); > > gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, src); > + gen_helper_fcvt_d_l(dest, cpu_env, src); > + gen_set_fpr_d(ctx, a->rd, dest); > > mark_fs_dirty(ctx); > return true; > @@ -407,12 +533,15 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, > arg_fcvt_d_lu *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_FPU; > - REQUIRE_EXT(ctx, RVD); > + REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd); > > + TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO); > > gen_set_rm(ctx, a->rm); > - gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, src); > + gen_helper_fcvt_d_lu(dest, cpu_env, src); > + gen_set_fpr_d(ctx, a->rd, dest); > > mark_fs_dirty(ctx); > return true; > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 10cf37be41..fac998a6b5 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -416,6 +416,31 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int > reg_num) > } > } > > +static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) > +{ > + if (!ctx->cfg_ptr->ext_zfinx) { > + return cpu_fpr[reg_num]; > + } > + > + if (reg_num == 0) { > + return tcg_constant_i64(0); > + } > + switch (get_xl(ctx)) { > + case MXL_RV32: > + { > + TCGv_i64 t = ftemp_new(ctx); > + tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); > + return t; > + } > +#ifdef TARGET_RISCV64 > + case MXL_RV64: > + return cpu_gpr[reg_num]; > +#endif > + default: > + g_assert_not_reached(); > + } > +} > + > static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) > { > if (!ctx->cfg_ptr->ext_zfinx) { > @@ -463,6 +488,33 @@ static void gen_set_fpr_hs(DisasContext *ctx, int > reg_num, TCGv_i64 t) > } > } > > +static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) > +{ > + if (!ctx->cfg_ptr->ext_zfinx) { > + tcg_gen_mov_i64(cpu_fpr[reg_num], t); > + return; > + } > + > + if (reg_num != 0) { > + switch (get_xl(ctx)) { > + case MXL_RV32: > +#ifdef TARGET_RISCV32 > + tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); > + break; > +#else > + tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); > + tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); > + break; > + case MXL_RV64: > + tcg_gen_mov_i64(cpu_gpr[reg_num], t); > + break; > +#endif > + default: > + g_assert_not_reached(); > + } > + } > +} > + > static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) > { > target_ulong next_pc; > -- > 2.17.1 > >
