This is useful to analyze changes in the U-Boot RAM driver when SDRAM
training is performed.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
hw/misc/aspeed_sdmc.c | 2 ++
hw/misc/trace-events | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 08f856cbda7e..d2a3931033b3 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -130,6 +130,7 @@ static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr,
unsigned size)
return 0;
}
+ trace_aspeed_sdmc_read(addr, s->regs[addr]);
return s->regs[addr];
}
@@ -148,6 +149,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr,
uint64_t data,
return;
}
+ trace_aspeed_sdmc_write(addr, data);
asc->write(s, addr, data);
}
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 1c373dd0a4c5..fb5a3897807f 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -205,6 +205,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C
write: offset 0x%" PRIx64
aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C
Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64
aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data)
"I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64
+# aspeed_sdmc.c
+aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%"
PRIx64
+aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x%"
PRIx64
+
# bcm2835_property.c
bcm2835_mbox_property(uint32_t tag, uint32_t bufsize, size_t resplen) "mbox
property tag:0x%08x in_sz:%u out_sz:%zu"
--
2.34.1
