This is the series of patches to introduce RISC-V IOMMU emulation in QEMU. The Rivos IOMMU device implementation is based on a draft proposal of a RISC-V I/O Management Unit (IOMMU) [1] as published on 2022/03/10, shared and discussed with RISCV-V IOMMU Task Group [2].
Specification is in *draft* stage and is expected to be changed based on discussion and feedback received from RISC-V IOMMU TG. This series enables rivos-iommu support for riscv/virt machine emulation. With corresponding Linux kernel driver and (modified) pending AIA-IMSIC support [3] QEMU is able to boot into Linux with I/O protection enabled for PCIe devices. Without AIA-IMSIC support interrupt based I/O translation fault reporting and MSI remapping features are not available, while all remaining IOMMU features are active. To enable IOMMU in QEMU add 'rivos-iommu' to the device list for 'virt' machine emulation. [1] https://docs.google.com/document/d/1ytBZ6eDk1pAeBlZjDvm6_qqJbKQ0fMYKedyx0uoAGB0/view [2] https://lists.riscv.org/g/tech-iommu/message/3 [3] https://lore.kernel.org/qemu-devel/20220220085526.808674-1-a...@brainfault.org Tomasz Jeznach (2): hw/riscv: rivos-iommu: Baseline implementation of RIVOS IOMMU. hw/riscv: virt: Add rivos-iommu device to 'virt' machine. hw/riscv/Kconfig | 4 + hw/riscv/meson.build | 1 + hw/riscv/rivos_iommu.c | 1350 ++++++++++++++++++++++++++++++++ hw/riscv/trace-events | 7 + hw/riscv/trace.h | 2 + hw/riscv/virt.c | 115 ++- include/hw/pci/pci_ids.h | 1 + include/hw/riscv/rivos_iommu.h | 80 ++ include/hw/riscv/virt.h | 2 + meson.build | 1 + 10 files changed, 1539 insertions(+), 24 deletions(-) create mode 100644 hw/riscv/rivos_iommu.c create mode 100644 hw/riscv/trace-events create mode 100644 hw/riscv/trace.h create mode 100644 include/hw/riscv/rivos_iommu.h -- 2.25.1
