Hi,
On 2022/3/29 上午5:02, Mark Cave-Ayland wrote:
+static const MemoryRegionOps loongarch_qemu_ops = {
+ .read = loongarch_qemu_read,
+ .write = loongarch_qemu_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
The implementation above doesn't actually support access size 4; it
only supports 8.
It doesn't seem like this should be a io region at all, but a ROM.
Strangely enough I had a similar requirement for my q800 patches, and
when I tried to implement a ROM memory region then the accesses didn't
work as expected. I can't remember the exact problem however...
It seems that iocsr_misc may not use rom region, because the
MISC_FUNC_REG should be writen.
could I modify it as a device? and define its structure and memregion
options.
Thanks
Xiaojuan
