On Tue, 5 Apr 2022 at 23:38, Hao Wu <wuhao...@google.com> wrote: > > The NPCM8xx GCR device can be accessed with 64-bit memory operations. > This patch supports that. > > Signed-off-by: Hao Wu <wuhao...@google.com> > Reviewed-by: Patrick Venture <vent...@google.com> > --- > hw/misc/npcm_gcr.c | 98 +++++++++++++++++++++++++++++++++----------- > hw/misc/trace-events | 4 +- > 2 files changed, 77 insertions(+), 25 deletions(-) > > diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c > index 14c298602a..aa81db23d7 100644 > --- a/hw/misc/npcm_gcr.c > +++ b/hw/misc/npcm_gcr.c > @@ -201,6 +201,7 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr > offset, unsigned size) > uint32_t reg = offset / sizeof(uint32_t); > NPCMGCRState *s = opaque; > NPCMGCRClass *c = NPCM_GCR_GET_CLASS(s); > + uint64_t value; > > if (reg >= c->nr_regs) { > qemu_log_mask(LOG_GUEST_ERROR, > @@ -209,9 +210,23 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr > offset, unsigned size) > return 0; > } > > - trace_npcm_gcr_read(offset, s->regs[reg]); > + switch (size) { > + case 4: > + value = s->regs[reg]; > + break; > + > + case 8: > + value = s->regs[reg] + (((uint64_t)s->regs[reg + 1]) << 32); > + break; > + > + default: > + g_assert_not_reached(); > + } > > - return s->regs[reg]; > + if (s->regs[reg] != 0) {
Why are we now only tracing the read if it's not 0 ? > + trace_npcm_gcr_read(offset, value); > + } > + return value; > } -- PMM