On Tue, 26 Apr 2022 at 12:51, Lucas Mateus Castro(alqotel) <lucas.ara...@eldorado.org.br> wrote: > > From: "Lucas Mateus Castro (alqotel)" <lucas.ara...@eldorado.org.br> > > This patch series is an RFC of the Matrix-Multiply Assist (MMA) > instructions implementation from the PowerISA 3.1 > > These and the VDIV/VMOD implementation are the last new PowerISA 3.1 > instructions left to be implemented. > > Thanks > Lucas Mateus Castro (alqotel) (7): > target/ppc: Implement xxm[tf]acc and xxsetaccz > target/ppc: Implemented xvi*ger* instructions > target/ppc: Implemented pmxvi*ger* instructions > target/ppc: Implemented xvf*ger* > target/ppc: Implemented xvf16ger* > target/ppc: Implemented pmxvf*ger* > target/ppc: Implemented [pm]xvbf16ger2*
I have a small test case for the MMA instructions that Alistair wrote a while back[1]. It passes when run with these patches applied (previously it would sigill). $ qemu-ppc64le -cpu power10 -L ~/ppc64le/ ./test -m Smoke test MMA MMA[0] = 1 (Correct) MMA[1] = 2 (Correct) MMA[2] = 3 (Correct) MMA[3] = 4 (Correct) MMA[4] = 2 (Correct) MMA[5] = 4 (Correct) MMA[6] = 6 (Correct) MMA[7] = 8 (Correct) MMA[8] = 3 (Correct) MMA[9] = 6 (Correct) MMA[10] = 9 (Correct) MMA[11] = 12 (Correct) MMA[12] = 4 (Correct) MMA[13] = 8 (Correct) MMA[14] = 12 (Correct) MMA[15] = 16 (Correct) [1] https://github.com/shenki/p10_tests > > include/fpu/softfloat.h | 9 ++ > target/ppc/cpu.h | 15 +++ > target/ppc/fpu_helper.c | 130 ++++++++++++++++++ > target/ppc/helper.h | 7 + > target/ppc/insn32.decode | 49 +++++++ > target/ppc/insn64.decode | 80 +++++++++++ > target/ppc/int_helper.c | 85 ++++++++++++ > target/ppc/internal.h | 28 ++++ > target/ppc/translate/vsx-impl.c.inc | 200 ++++++++++++++++++++++++++++ > 9 files changed, 603 insertions(+) > > -- > 2.31.1 > >
