On Wed, May 4, 2022 at 6:02 AM Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> We already have some larger ifdef blocks for ARM and RISCV;
> split out a boolean test for SYS_SYNCCACHE.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> semihosting/arm-compat-semi.c | 20 +++++++++++++-------
> 1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
> index b2816e9f66..6149be404f 100644
> --- a/semihosting/arm-compat-semi.c
> +++ b/semihosting/arm-compat-semi.c
> @@ -224,6 +224,12 @@ static inline target_ulong
> common_semi_stack_bottom(CPUState *cs)
> CPUARMState *env = &cpu->env;
> return is_a64(env) ? env->xregs[31] : env->regs[13];
> }
> +
> +static inline bool common_semi_has_synccache(CPUArchState *env)
> +{
> + /* Invalid for A32/T32. */
> + return !is_a64(env);
> +}
> #endif /* TARGET_ARM */
>
> #ifdef TARGET_RISCV
> @@ -260,6 +266,11 @@ static inline target_ulong
> common_semi_stack_bottom(CPUState *cs)
> CPURISCVState *env = &cpu->env;
> return env->gpr[xSP];
> }
> +
> +static inline bool common_semi_has_synccache(CPUArchState *env)
> +{
> + return true;
> +}
> #endif
>
> /*
> @@ -1103,16 +1114,11 @@ void do_common_semihosting(CPUState *cs)
> * virtual address range. This is a nop for us since we don't
> * implement caches. This is only present on A64.
> */
> -#ifdef TARGET_ARM
> - if (is_a64(cs->env_ptr)) {
> + if (common_semi_has_synccache(env)) {
> common_semi_set_ret(cs, 0);
> break;
> }
> -#endif
> -#ifdef TARGET_RISCV
> - common_semi_set_ret(cs, 0);
> -#endif
> - /* fall through -- invalid for A32/T32 */
> + /* fall through */
> default:
> fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
> cpu_dump_state(cs, stderr, 0);
> --
> 2.34.1
>
>
