On Fri, Apr 29, 2022 at 8:20 PM Frank Chang <frank.ch...@sifive.com> wrote:
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>
>
> On Fri, Apr 29, 2022 at 11:34 AM Anup Patel <apa...@ventanamicro.com>
> wrote:
>
>> When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
>> the riscv_csrrw_check() function should generate virtual instruction
>> trap instead illegal instruction trap.
>>
>> Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum for
>> CSR access")
>>
>
This is not the correct Fixes tag. This patch just changed the error code
to enum.
The above said issue exists before this patch.
I think the correct fix should be 0a42f4c44088 (" target/riscv: Fix CSR
perm checking for HS mode"). No ?
> Signed-off-by: Anup Patel <apa...@ventanamicro.com>
>> ---
>> target/riscv/csr.c | 8 ++++++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 3500e07f92..2bf0a97196 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -3139,7 +3139,7 @@ static inline RISCVException
>> riscv_csrrw_check(CPURISCVState *env,
>> int read_only = get_field(csrno, 0xC00) == 3;
>> int csr_min_priv = csr_ops[csrno].min_priv_ver;
>> #if !defined(CONFIG_USER_ONLY)
>> - int effective_priv = env->priv;
>> + int csr_priv, effective_priv = env->priv;
>>
>> if (riscv_has_ext(env, RVH) &&
>> env->priv == PRV_S &&
>> @@ -3152,7 +3152,11 @@ static inline RISCVException
>> riscv_csrrw_check(CPURISCVState *env,
>> effective_priv++;
>> }
>>
>> - if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
>> + csr_priv = get_field(csrno, 0x300);
>> + if (!env->debugger && (effective_priv < csr_priv)) {
>> + if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) {
>> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>> + }
>> return RISCV_EXCP_ILLEGAL_INST;
>> }
>> #endif
>> --
>> 2.34.1
>>
>>
>>
--
Regards,
Atish
