This patch adds RISC-V Zihintpause support. The extension is set to be enabled by default and opcode has been added to insn32.decode.
Added trans_pause for TCG to mainly be a no-op and break reservation. The change can also be found in: https://github.com/dlu42/qemu/tree/zihintpause_support_v1 Tested along with pause support added to cpu_relax function for linux, the changes I made to linux to test can be found here: https://github.com/dlu42/linux/tree/pause_support_v1 Dao Lu (1): Add Zihintpause support target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 7 ++++++- target/riscv/insn_trans/trans_rvi.c.inc | 18 ++++++++++++++++++ 4 files changed, 27 insertions(+), 1 deletion(-) -- 2.36.0
