Make sure 'tcg_gen_debug_insn_start' is always called in 'gen_intermediate_code_internal' and after calls to 'gen_io_start' (before the instruction decoding).
Signed-off-by: Lluís Vilanova <vilan...@ac.upc.edu> --- target-alpha/translate.c | 11 ++++++----- target-cris/translate.c | 12 +++++++----- target-i386/translate.c | 5 +++-- target-lm32/translate.c | 7 +++---- target-m68k/translate.c | 6 +++++- target-microblaze/translate.c | 6 +++--- target-mips/translate.c | 6 +++--- target-ppc/translate.c | 6 ++++-- target-s390x/translate.c | 4 ++++ target-sh4/translate.c | 8 ++++---- target-sparc/translate.c | 6 ++++-- target-unicore32/translate.c | 3 +++ target-xtensa/translate.c | 7 +++---- 13 files changed, 52 insertions(+), 35 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 18f5428..5efc605 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3389,15 +3389,16 @@ static inline void gen_intermediate_code_internal(CPUState *env, gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } - if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); - insn = ldl_code(ctx.pc); - num_insns++; - - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { tcg_gen_debug_insn_start(ctx.pc); } + insn = ldl_code(ctx.pc); + num_insns++; + ctx.pc += 4; ret = translate_one(ctxp, insn); diff --git a/target-cris/translate.c b/target-cris/translate.c index cac22c9..f6bebea 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3080,9 +3080,6 @@ static unsigned int crisv32_decoder(DisasContext *dc) int insn_len = 2; int i; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(dc->pc); - /* Load a halfword onto the instruction register. */ dc->ir = cris_fetch(dc, dc->pc, 2, 0); @@ -3291,9 +3288,14 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); - dc->clear_x = 1; + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } + + dc->clear_x = 1; + + insn_len = dc->decoder(dc); - insn_len = dc->decoder(dc); dc->ppc = dc->pc; dc->pc += insn_len; if (dc->clear_x) diff --git a/target-i386/translate.c b/target-i386/translate.c index 7192ce9..9818ebb 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4081,8 +4081,6 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) target_ulong next_eip, tval; int rex_w, rex_r; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(pc_start); s->pc = pc_start; prefixes = 0; aflag = s->code32; @@ -7822,6 +7820,9 @@ static inline void gen_intermediate_code_internal(CPUState *env, } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(pc_ptr); + } pc_ptr = disas_insn(dc, pc_ptr); num_insns++; diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 2535fb7..c0d9195 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -952,10 +952,6 @@ static inline void decode(DisasContext *dc) { uint32_t ir; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { - tcg_gen_debug_insn_start(dc->pc); - } - dc->ir = ir = ldl_code(dc->pc); LOG_DIS("%8.8x\t", dc->ir); @@ -1076,6 +1072,9 @@ static void gen_intermediate_code_internal(CPUState *env, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } decode(dc); dc->pc += 4; diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 9cb8139..5e735f3 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3018,8 +3018,12 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } + dc->insn_pc = dc->pc; - disas_m68k_insn(env, dc); + disas_m68k_insn(env, dc); num_insns++; } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end && !env->singlestep_enabled && diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 6b6a593..a1a9ce6 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1550,9 +1550,6 @@ static inline void decode(DisasContext *dc) uint32_t ir; int i; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(dc->pc); - dc->ir = ir = ldl_code(dc->pc); LOG_DIS("%8.8x\t", dc->ir); @@ -1686,6 +1683,9 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } dc->clear_imm = 1; decode(dc); diff --git a/target-mips/translate.c b/target-mips/translate.c index 0076058..6f67b36 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -11715,9 +11715,6 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch) gen_set_label(l1); } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(ctx->pc); - op = MASK_OP_MAJOR(ctx->opcode); rs = (ctx->opcode >> 21) & 0x1f; rt = (ctx->opcode >> 16) & 0x1f; @@ -12444,6 +12441,9 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(ctx.pc); + } is_branch = 0; if (!(ctx.hflags & MIPS_HFLAG_M16)) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index af78360..c515ea4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9490,6 +9490,10 @@ static inline void gen_intermediate_code_internal(CPUState *env, ctx.nip, ctx.mem_idx, (int)msr_ir); if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(ctx.nip); + } + if (unlikely(ctx.le_mode)) { ctx.opcode = bswap32(ldl_code(ctx.nip)); } else { @@ -9498,8 +9502,6 @@ static inline void gen_intermediate_code_internal(CPUState *env, LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), little_endian ? "little" : "big"); - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(ctx.nip); ctx.nip += 4; table = env->opcodes; num_insns++; diff --git a/target-s390x/translate.c b/target-s390x/translate.c index c2a04a5..f0b877e 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5174,6 +5174,10 @@ static inline void gen_intermediate_code_internal(CPUState *env, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc.pc); + } + #if defined(S390X_DEBUG_DISAS_VERBOSE) LOG_DISAS("pc " TARGET_FMT_lx "\n", dc.pc); diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d75c065..6c1872c 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1904,10 +1904,6 @@ static void decode_opc(DisasContext * ctx) { uint32_t old_flags = ctx->flags; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { - tcg_gen_debug_insn_start(ctx->pc); - } - _decode_opc(ctx); if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { @@ -1995,6 +1991,10 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(ctx.pc); + } + #if 0 fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); fflush(stderr); diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 415d996..5c7cca0 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2381,8 +2381,6 @@ static void disas_sparc_insn(DisasContext * dc) TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; target_long simm; - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(dc->pc); insn = ldl_code(dc->pc); opc = GET_FIELD(insn, 0, 1); @@ -5297,6 +5295,10 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } + last_pc = dc->pc; disas_sparc_insn(dc); num_insns++; diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 8edca98..74172ea 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1920,6 +1920,9 @@ static inline void gen_intermediate_code_internal(CPUState *env, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } disas_uc32_insn(env, dc); diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 3f741ac..96db089 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2458,15 +2458,14 @@ static void gen_intermediate_code_internal( gen_opc_icount[lj] = insn_count; } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { - tcg_gen_debug_insn_start(dc.pc); - } - ++dc.ccount_delta; if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc.pc); + } disas_xtensa_insn(&dc); ++insn_count;