Víctor Colombo <victor.colo...@eldorado.org.br> writes:
> FPSCR_* bit values in QEMU are in the 'inverted' order from what Power
> ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h).
> Now that PPC_BIT_NR macro was introduced to fix this situation for the
> MSR bits, we can use it for the FPSCR bits too.
>
> Also, adjust the comments to make then fit in 80 columns
>
> Signed-off-by: Víctor Colombo <victor.colo...@eldorado.org.br>
Apart form the typo below.
Reviewed-by: Fabiano Rosas <faro...@linux.ibm.com>
> ---
> target/ppc/cpu.h | 72 ++++++++++++++++++++++++------------------------
> 1 file changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 6d78078f37..c78f64cced 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -694,42 +694,42 @@ enum {
<snip>
> +#define FPSCR_DRN2 PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl.
> */
> +#define FPSCR_DRN1 PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl.
> */
> +#define FPSCR_DRN0 PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl.
> */
> +#define FPSCR_FX PPC_BIT_NR(32) /* Floating-point exception summary
> */
> +#define FPSCR_FEX PPC_BIT_NR(33) /* Floating-point enabled exception
> summ.*/
> +#define FPSCR_VX PPC_BIT_NR(34) /* Floating-point invalid op. excp.
> summ.*/
> +#define FPSCR_OX PPC_BIT_NR(35) /* Floating-point overflow exception
> */
> +#define FPSCR_UX PPC_BIT_NR(36) /* Floating-point underflow exceptio
> */
exception
> +#define FPSCR_ZX PPC_BIT_NR(37) /* Floating-point zero divide exception
> */
> +#define FPSCR_XX PPC_BIT_NR(38) /* Floating-point inexact exception
> */
> +#define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp
> (sNan)*/
> +#define FPSCR_VXISI PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf)
> */
> +#define FPSCR_VXIDI PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf)
> */
> +#define FPSCR_VXZDZ PPC_BIT_NR(42) /* Floating-point invalid op. excp
> (zero)*/
> +#define FPSCR_VXIMZ PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf)
> */
> +#define FPSCR_VXVC PPC_BIT_NR(44) /* Floating-point invalid op. excp
> (comp)*/
> +#define FPSCR_FR PPC_BIT_NR(45) /* Floating-point fraction rounded
> */
> +#define FPSCR_FI PPC_BIT_NR(46) /* Floating-point fraction inexact
> */
> +#define FPSCR_C PPC_BIT_NR(47) /* Floating-point result class
> descriptor*/
> +#define FPSCR_FL PPC_BIT_NR(48) /* Floating-point less than or negative
> */
> +#define FPSCR_FG PPC_BIT_NR(49) /* Floating-point greater than or neg.
> */
> +#define FPSCR_FE PPC_BIT_NR(50) /* Floating-point equal or zero
> */
> +#define FPSCR_FU PPC_BIT_NR(51) /* Floating-point unordered or NaN
> */
> +#define FPSCR_FPCC PPC_BIT_NR(51) /* Floating-point condition code
> */
> +#define FPSCR_FPRF PPC_BIT_NR(51) /* Floating-point result flags
> */
> +#define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp
> (soft)*/
> +#define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp
> (sqrt)*/
> +#define FPSCR_VXCVI PPC_BIT_NR(55) /* Floating-point invalid op. excp (int)
> */
> +#define FPSCR_VE PPC_BIT_NR(56) /* Floating-point invalid op. excp
> enable*/
> +#define FPSCR_OE PPC_BIT_NR(57) /* Floating-point overflow excp. enable
> */
> +#define FPSCR_UE PPC_BIT_NR(58) /* Floating-point underflow excp. enable
> */
> +#define FPSCR_ZE PPC_BIT_NR(59) /* Floating-point zero divide excp
> enable*/
> +#define FPSCR_XE PPC_BIT_NR(60) /* Floating-point inexact excp. enable
> */
> +#define FPSCR_NI PPC_BIT_NR(61) /* Floating-point non-IEEE mode
> */
> +#define FPSCR_RN1 PPC_BIT_NR(62)
> +#define FPSCR_RN0 PPC_BIT_NR(63) /* Floating-point rounding control
> */
> /* Invalid operation exception summary */
> #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
> (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
