On 6/29/22 13:28, Víctor Colombo wrote:
Hello everyone, Set of patches containing implementations for some instructions that were missing before. Also, moves some related instructions to decodetree. Add mffsce test.
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel
v3: - Rebase on master - Add r-b v2: - Added R-b on patches 1, 8, 10, and 11. Dropped the R-b on some of the patches as there were big changes on them. - Fixed addg6s issues - Separated do_mffsc in two different, more specialized functions - Changed mffs* patches order to make it more readable, as suggested by Richard - Added a new patch with a test for the mffsce instruction Matheus Ferst (4): target/ppc: Add flag for ISA v2.06 BCDA instructions target/ppc: implement addg6s target/ppc: implement cbcdtd target/ppc: implement cdtbcd Víctor Colombo (7): target/ppc: Fix insn32.decode style issues target/ppc: Move mffscrn[i] to decodetree target/ppc: Move mffsce to decodetree target/ppc: Move mffsl to decodetree target/ppc: Move mffs[.] to decodetree target/ppc: Implement mffscdrn[i] instructions tests/tcg/ppc64: Add mffsce test target/ppc/cpu.h | 5 +- target/ppc/cpu_init.c | 10 +- target/ppc/dfp_helper.c | 65 +++++++ target/ppc/helper.h | 2 + target/ppc/insn32.decode | 55 ++++-- target/ppc/internal.h | 3 - target/ppc/translate/fixedpoint-impl.c.inc | 51 ++++++ target/ppc/translate/fp-impl.c.inc | 203 ++++++++++++--------- target/ppc/translate/fp-ops.c.inc | 9 - tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/ppc64le/Makefile.target | 1 + tests/tcg/ppc64le/mffsce.c | 37 ++++ 12 files changed, 322 insertions(+), 120 deletions(-) create mode 100644 tests/tcg/ppc64le/mffsce.c
