Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
hw/ppc/ppc405.h | 14 ++++++++++
hw/ppc/ppc405_uc.c | 67 +++++++++++++++++++++++++++++++++-------------
2 files changed, 62 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 8acb90427596..8ca32f35ce67 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t {
typedef struct Ppc405SoCState Ppc405SoCState;
+/* Peripheral local bus arbitrer */
+#define TYPE_PPC405_PLB "ppc405-plb"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
+struct Ppc405PlbState {
+ DeviceState parent_obj;
+
+ PowerPCCPU *cpu;
+
+ uint32_t acr;
+ uint32_t bear;
+ uint32_t besr;
+};
+
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@@ -245,6 +258,7 @@ struct Ppc405SoCState {
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
+ Ppc405PlbState plb;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index ca214ee4d741..9bbd524ad5ea 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -148,19 +148,11 @@ enum {
PLB4A1_ACR = 0x089,
};
-typedef struct ppc4xx_plb_t ppc4xx_plb_t;
-struct ppc4xx_plb_t {
- uint32_t acr;
- uint32_t bear;
- uint32_t besr;
-};
-
static uint32_t dcr_read_plb (void *opaque, int dcrn)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
uint32_t ret;
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
ret = plb->acr;
@@ -182,9 +174,8 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn)
static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(opaque);
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
/* We don't care about the actual parameters written as
@@ -202,28 +193,55 @@ static void dcr_write_plb (void *opaque, int dcrn,
uint32_t val)
}
}
-static void ppc4xx_plb_reset (void *opaque)
+static void ppc405_plb_reset(DeviceState *dev)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(dev);
- plb = opaque;
plb->acr = 0x00000000;
plb->bear = 0x00000000;
plb->besr = 0x00000000;
}
-void ppc4xx_plb_init(CPUPPCState *env)
+static void ppc405_plb_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(dev);
+ CPUPPCState *env;
+
+ assert(plb->cpu);
+
+ env = &plb->cpu->env;
- plb = g_new0(ppc4xx_plb_t, 1);
ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- qemu_register_reset(ppc4xx_plb_reset, plb);
+}
+
+static Property ppc405_plb_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc405PlbState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_plb_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_plb_realize;
+ dc->user_creatable = false;
+ dc->reset = ppc405_plb_reset;
+ device_class_set_props(dc, ppc405_plb_properties);
+}
+
+void ppc4xx_plb_init(CPUPPCState *env)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ DeviceState *dev = qdev_new(TYPE_PPC405_EBC);
+
+ object_property_set_link(OBJECT(cpu), "cpu", OBJECT(dev), &error_abort);
+ qdev_realize_and_unref(dev, NULL, &error_fatal);
}
/*****************************************************************************/
@@ -1446,6 +1464,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
+
+ object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
}
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1484,7 +1504,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error
**errp)
}
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ object_property_set_link(OBJECT(&s->plb), "cpu", OBJECT(&s->cpu),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&s->plb), NULL, errp)) {
+ return;
+ }
/* PLB to OPB bridge */
object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu),
@@ -1615,6 +1639,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void
*data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_PLB,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Ppc405PlbState),
+ .class_init = ppc405_plb_class_init,
+ }, {
.name = TYPE_PPC405_POB,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405PobState),
--
2.37.1
