On 8/9/22 19:34, BALATON Zoltan wrote:
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
hw/ppc/ppc405.h | 1 +
include/hw/ppc/ppc4xx.h | 32 +++++++++-
hw/ppc/ppc405_uc.c | 18 ++++--
hw/ppc/ppc4xx_devs.c | 135 ++++++++++++++++++----------------------
hw/ppc/sam460ex.c | 16 +++--
5 files changed, 116 insertions(+), 86 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index cb34792daf6b..31c94e474209 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -244,6 +244,7 @@ struct Ppc405SoCState {
Ppc405OpbaState opba;
Ppc405PobState pob;
Ppc405PlbState plb;
+ Ppc4xxMalState mal;
};
/* PowerPC 405 core */
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 82e60b0e0742..acd096cb2394 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -26,6 +26,7 @@
#define PPC4XX_H
#include "hw/ppc/ppc.h"
+#include "hw/sysbus.h"
This looks odd to me as no line added below seems to need it.
It is a leftover.
Thanks,
C.
