The RISC-V specification specifies imm12, rs1 and rd to be all-zeros, so we can't ignore these bits when decoding into fence.i.
Update the decode pattern to reflect the specification. Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu> --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 014127d066..089128c3dc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -151,7 +151,7 @@ sra 0100000 ..... ..... 101 ..... 0110011 @r or 0000000 ..... ..... 110 ..... 0110011 @r and 0000000 ..... ..... 111 ..... 0110011 @r fence ---- pred:4 succ:4 ----- 000 ----- 0001111 -fence_i ---- ---- ---- ----- 001 ----- 0001111 +fence_i 000000000000 00000 001 00000 0001111 csrrw ............ ..... 001 ..... 1110011 @csr csrrs ............ ..... 010 ..... 1110011 @csr csrrc ............ ..... 011 ..... 1110011 @csr -- 2.34.1
