For simplicity, this also brings in the entire implementation of ALU operations from the old decoder.
Signed-off-by: Paolo Bonzini <[email protected]> --- target/i386/tcg/decode-new.c.inc | 16 +++++ target/i386/tcg/emit.c.inc | 109 +++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc index b53afea9c8..6d0d6a683c 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -464,8 +464,24 @@ static void decode_twobyte(DisasContext *s, CPUX86State *env, X86OpEntry *entry, static X86OpEntry A2_00_F7[16][8] = { { + X86_OP_ENTRY2(ADD, E,b, G,b), + X86_OP_ENTRY2(ADD, E,v, G,v), + X86_OP_ENTRY2(ADD, G,b, E,b), + X86_OP_ENTRY2(ADD, G,v, E,v), + X86_OP_ENTRY2(ADD, 0,b, I,b), /* AL, Ib */ + X86_OP_ENTRY2(ADD, 0,v, I,z), /* rAX, Iz */ + X86_OP_ENTRYr(PUSH, ES, w, i64), + X86_OP_ENTRYw(POP, ES, w, i64) }, { + X86_OP_ENTRY2(ADC, E,b, G,b), + X86_OP_ENTRY2(ADC, E,v, G,v), + X86_OP_ENTRY2(ADC, G,b, E,b), + X86_OP_ENTRY2(ADC, G,v, E,v), + X86_OP_ENTRY2(ADC, 0,b, I,b), /* AL, Ib */ + X86_OP_ENTRY2(ADC, 0,v, I,z), /* rAX, Iz */ + X86_OP_ENTRYr(PUSH, SS, w, i64), + X86_OP_ENTRYw(POP, SS, w, i64) }, { }, diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 93d14ff793..758e468a25 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -38,6 +38,115 @@ static void gen_load(DisasContext *s, TCGv v, X86DecodedOp *op, uint64_t imm) op->v = v; } +static void gen_alu_op(DisasContext *s1, int op, MemOp ot) +{ + switch(op) { + case OP_ADCL: + gen_compute_eflags_c(s1, s1->tmp4); + if (s1->prefix & PREFIX_LOCK) { + tcg_gen_add_tl(s1->T0, s1->tmp4, s1->T1); + tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0, + s1->mem_index, ot | MO_LE); + } else { + tcg_gen_add_tl(s1->T0, s1->T0, s1->T1); + tcg_gen_add_tl(s1->T0, s1->T0, s1->tmp4); + } + gen_op_update3_cc(s1, s1->tmp4); + set_cc_op(s1, CC_OP_ADCB + ot); + break; + case OP_SBBL: + gen_compute_eflags_c(s1, s1->tmp4); + if (s1->prefix & PREFIX_LOCK) { + tcg_gen_add_tl(s1->T0, s1->T1, s1->tmp4); + tcg_gen_neg_tl(s1->T0, s1->T0); + tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0, + s1->mem_index, ot | MO_LE); + } else { + tcg_gen_sub_tl(s1->T0, s1->T0, s1->T1); + tcg_gen_sub_tl(s1->T0, s1->T0, s1->tmp4); + } + gen_op_update3_cc(s1, s1->tmp4); + set_cc_op(s1, CC_OP_SBBB + ot); + break; + case OP_ADDL: + if (s1->prefix & PREFIX_LOCK) { + tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T1, + s1->mem_index, ot | MO_LE); + } else { + tcg_gen_add_tl(s1->T0, s1->T0, s1->T1); + } + gen_op_update2_cc(s1); + set_cc_op(s1, CC_OP_ADDB + ot); + break; + case OP_SUBL: + if (s1->prefix & PREFIX_LOCK) { + tcg_gen_neg_tl(s1->T0, s1->T1); + tcg_gen_atomic_fetch_add_tl(s1->cc_srcT, s1->A0, s1->T0, + s1->mem_index, ot | MO_LE); + tcg_gen_sub_tl(s1->T0, s1->cc_srcT, s1->T1); + } else { + tcg_gen_mov_tl(s1->cc_srcT, s1->T0); + tcg_gen_sub_tl(s1->T0, s1->T0, s1->T1); + } + gen_op_update2_cc(s1); + set_cc_op(s1, CC_OP_SUBB + ot); + break; + default: + case OP_ANDL: + if (s1->prefix & PREFIX_LOCK) { + tcg_gen_atomic_and_fetch_tl(s1->T0, s1->A0, s1->T1, + s1->mem_index, ot | MO_LE); + } else { + tcg_gen_and_tl(s1->T0, s1->T0, s1->T1); + } + gen_op_update1_cc(s1); + set_cc_op(s1, CC_OP_LOGICB + ot); + break; + case OP_ORL: + if (s1->prefix & PREFIX_LOCK) { + tcg_gen_atomic_or_fetch_tl(s1->T0, s1->A0, s1->T1, + s1->mem_index, ot | MO_LE); + } else { + tcg_gen_or_tl(s1->T0, s1->T0, s1->T1); + } + gen_op_update1_cc(s1); + set_cc_op(s1, CC_OP_LOGICB + ot); + break; + case OP_XORL: + if (s1->prefix & PREFIX_LOCK) { + tcg_gen_atomic_xor_fetch_tl(s1->T0, s1->A0, s1->T1, + s1->mem_index, ot | MO_LE); + } else { + tcg_gen_xor_tl(s1->T0, s1->T0, s1->T1); + } + gen_op_update1_cc(s1); + set_cc_op(s1, CC_OP_LOGICB + ot); + break; + } +} + +static void gen_ADC(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_alu_op(s, OP_ADCL, decode->op[0].ot); +} + +static void gen_ADD(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_alu_op(s, OP_ADDL, decode->op[0].ot); +} + +static void gen_PUSH(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + gen_push_v(s, decode->op[2].v); +} + +static void gen_POP(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +{ + MemOp ot = gen_pop_T0(s); + /* NOTE: order is important for pop %sp */ + gen_pop_update(s, ot); +} + static void gen_writeback(DisasContext *s, X86DecodedOp *op) { switch (op->alu_op_type) { -- 2.37.1
