Peter Maydell <peter.mayd...@linaro.org> writes:
> On Mon, 26 Sept 2022 at 14:39, Alex Bennée <alex.ben...@linaro.org> wrote: >> >> Now that MxTxAttrs encodes a CPU we should use that to figure it out. >> This solves edge cases like accessing via gdbstub or qtest. >> >> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> >> Signed-off-by: Alex Bennée <alex.ben...@linaro.org> >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 >> >> --- >> v2 >> - update for new field >> - bool asserts >> --- >> hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- >> 1 file changed, 22 insertions(+), 17 deletions(-) >> >> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c >> index 492b2421ab..d907df3884 100644 >> --- a/hw/intc/arm_gic.c >> +++ b/hw/intc/arm_gic.c >> @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { >> 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 >> }; >> >> -static inline int gic_get_current_cpu(GICState *s) >> +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) >> { >> - if (!qtest_enabled() && s->num_cpu > 1) { >> - return current_cpu->cpu_index; >> - } >> - return 0; >> + /* >> + * Something other than a CPU accessing the GIC would be a bug as >> + * would a CPU index higher than the GICState expects to be >> + * handling >> + */ >> + g_assert(attrs.requester_type == MEMTXATTRS_CPU); >> + g_assert(attrs.requester_id < s->num_cpu); > > Would it be a QEMU bug, or a guest code bug ? If it's possible > for the guest to mis-program a DMA controller to do a read that > goes through this function, we shouldn't assert. (Whether that > can happen will depend on how the board/SoC code puts together > the MemoryRegion hierarchy, I think.) Most likely a QEMU bug - how would a DMA master even access the GIC? > > thanks > -- PMM -- Alex Bennée
