icount trigger set an instruction count. After one instruction retired, the count will be decreased by 1. If the count decreased to 0, the icount trigger will fire.
icount trigger is needed by single step ptrace system call and the native GDB. In this patch set, change the translation when icount trigger enabled in the way that instruction executes one by one. After executing one instruction, call a helper function to decrease the count for itrigger. It also provides an accelebrated way. If QEMU executes with -icount parameter, itrigger is simulated by a timer with the count in itrigger as the deadline. Note the count in itrigger will only decrease when the priviledge matches, which is also processed in this patch set. After merging this patch set, QEMU will support type2/type6 trigger(needed by breakpoint and watchpoint) and icount trigger(needed by single step), which is enough for a PoC of native debug. LIU Zhiwei (4): target/riscv: Add itrigger support when icount is not enabled target/riscv: Add itrigger support when icount is enabled target/riscv: Enable native debug itrigger target/riscv: Add itrigger_enabled field to CPURISCVState target/riscv/cpu.h | 5 + target/riscv/cpu_helper.c | 8 + target/riscv/debug.c | 205 ++++++++++++++++++ target/riscv/debug.h | 13 ++ target/riscv/helper.h | 2 + .../riscv/insn_trans/trans_privileged.c.inc | 4 +- target/riscv/insn_trans/trans_rvi.c.inc | 8 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 +- target/riscv/machine.c | 15 ++ target/riscv/translate.c | 33 ++- 10 files changed, 286 insertions(+), 11 deletions(-) -- 2.17.1
