> 2022年10月29日 18:44，Philippe Mathieu-Daudé <phi...@linaro.org> 写道：
>
> On 29/10/22 04:00, Jiaxun Yang wrote:
>> As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX}
>> should is not writeable and hardcoded to 1.
>> Without those bits set, kernel is unable to access XKPHYS address
>> segmant. So just set them up on CPU reset.
>> Signed-off-by: Jiaxun Yang <jiaxun.y...@flygoat.com>
>> ---
>> target/mips/cpu.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
>> index d0a76b95f7..a870901bfa 100644
>> --- a/target/mips/cpu.c
>> +++ b/target/mips/cpu.c
>> @@ -304,6 +304,12 @@ static void mips_cpu_reset(DeviceState *dev)
>> env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
>> 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
>> env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
>> + if (env->insn_flags & INSN_LOONGSON2F) {
>> + /* Loongson-2F has those bits hardcoded to 1 */
>> + env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) |
>> + (1 << CP0St_UX);
>> + }
>
> Don't we want to update CP0_Status_rw_bitmask in Loongson-2F
> entry in mips_defs[] instead?
Write to those bits is already disabled by CP0_Status_rw_bitmask. However real
hardware
had those bits set to 1 but QEMU default them to 0…
Enable writing to those bits can also make kernel work but it mismatches actual
hardware
behavior.
Thanks.
---
Jiaxun Yang
