Suggested-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Rui Wang <wang...@loongson.cn>
---
target/loongarch/cpu.h | 27 ++++++++++++-------
.../insn_trans/trans_privileged.c.inc | 4 +--
target/loongarch/tlb_helper.c | 4 +--
target/loongarch/translate.c | 7 ++++-
target/loongarch/translate.h | 3 ++-
5 files changed, 29 insertions(+), 16 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index dbce176564..026cd6bb52 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -14,6 +14,7 @@
#include "qemu/timer.h"
#include "exec/memory.h"
#include "hw/sysbus.h"
+#include "cpu-csr.h"
#define IOCSRF_TEMP 0
#define IOCSRF_NODECNT 1
@@ -373,24 +374,30 @@ struct LoongArchCPUClass {
* 0 for kernel mode, 3 for user mode.
* Define an extra index for DA(direct addressing) mode.
*/
-#define MMU_KERNEL_IDX 0
-#define MMU_USER_IDX 3
-#define MMU_DA_IDX 4
+#define MMU_PLV_KERNEL 0
+#define MMU_PLV_USER 3
+#define MMU_IDX_KERNEL MMU_PLV_KERNEL
+#define MMU_IDX_USER MMU_PLV_USER
+#define MMU_IDX_DA 4
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
+ return MMU_IDX_USER;
#else
- uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
-
- if (!pg) {
- return MMU_DA_IDX;
+ if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
+ return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
}
- return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+ return MMU_IDX_DA;
#endif
}
+/*
+ * LoongArch CPUs hardware flags.
+ */
+#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */
+#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
+
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
target_ulong *pc,
target_ulong *cs_base,
@@ -398,7 +405,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState
*env,
{
*pc = env->pc;
*cs_base = 0;
- *flags = cpu_mmu_index(env, false);
+ *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
}
void loongarch_cpu_list(void);
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc
b/target/loongarch/insn_trans/trans_privileged.c.inc
index 9c4dcbfcfb..40f82becb0 100644
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
@@ -159,7 +159,7 @@ static const CSRInfo csr_info[] = {
static bool check_plv(DisasContext *ctx)
{
- if (ctx->base.tb->flags == MMU_USER_IDX) {
+ if (ctx->plv == MMU_PLV_USER) {
generate_exception(ctx, EXCCODE_IPE);
return true;
}
@@ -335,7 +335,7 @@ TRANS(iocsrwr_d, gen_iocsrwr, gen_helper_iocsrwr_d)
static void check_mmu_idx(DisasContext *ctx)
{
- if (ctx->mem_idx != MMU_DA_IDX) {
+ if (ctx->mem_idx != MMU_IDX_DA) {
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
}
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index d2f8fb0c60..c6d1de50fe 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -170,8 +170,8 @@ static int get_physical_address(CPULoongArchState *env,
hwaddr *physical,
int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx)
{
- int user_mode = mmu_idx == MMU_USER_IDX;
- int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
+ int user_mode = mmu_idx == MMU_IDX_USER;
+ int kernel_mode = mmu_idx == MMU_IDX_KERNEL;
uint32_t plv, base_c, base_v;
int64_t addr_high;
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 6091772349..38ced69803 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -75,7 +75,12 @@ static void loongarch_tr_init_disas_context(DisasContextBase
*dcbase,
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
- ctx->mem_idx = ctx->base.tb->flags;
+ ctx->plv = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;
+ if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
+ ctx->mem_idx = ctx->plv;
+ } else {
+ ctx->mem_idx = MMU_IDX_DA;
+ }
/* Bound the number of insns to execute to those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index 9cc12512d1..6d2e382e8b 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -29,7 +29,8 @@ typedef struct DisasContext {
DisasContextBase base;
target_ulong page_start;
uint32_t opcode;
- int mem_idx;
+ uint16_t mem_idx;
+ uint16_t plv;
TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
--
2.38.1
