On 11/22/2022 10:12 AM -0800, Richard Henderson wrote: > On 11/21/22 18:48, Zhuojia Shen wrote: > > In CPUID registers exposed to userspace, some registers were missing > > and some fields were not exposed. This patch aligns exposed ID > > registers and their fields with what Linux exposes currently. > > > > Specifically, the following new ID registers/fields are exposed to > > userspace: > > > > ID_AA64PFR1_EL1.BT: bits 3-0 > > ID_AA64PFR1_EL1.MTE: bits 11-8 > > ID_AA64PFR1_EL1.SME: bits 27-24 > > > > ID_AA64ZFR0_EL1.SVEver: bits 3-0 > > ID_AA64ZFR0_EL1.AES: bits 7-4 > > ID_AA64ZFR0_EL1.BitPerm: bits 19-16 > > ID_AA64ZFR0_EL1.BF16: bits 23-20 > > ID_AA64ZFR0_EL1.SHA3: bits 35-32 > > ID_AA64ZFR0_EL1.SM4: bits 43-40 > > ID_AA64ZFR0_EL1.I8MM: bits 47-44 > > ID_AA64ZFR0_EL1.F32MM: bits 55-52 > > ID_AA64ZFR0_EL1.F64MM: bits 59-56 > > > > ID_AA64SMFR0_EL1.F32F32: bit 32 > > ID_AA64SMFR0_EL1.B16F32: bit 34 > > ID_AA64SMFR0_EL1.F16F32: bit 35 > > ID_AA64SMFR0_EL1.I8I32: bits 39-36 > > ID_AA64SMFR0_EL1.F64F64: bit 48 > > ID_AA64SMFR0_EL1.I16I64: bits 55-52 > > ID_AA64SMFR0_EL1.FA64: bit 63 > > > > ID_AA64MMFR0_EL1.ECV: bits 63-60 > > > > ID_AA64MMFR1_EL1.AFP: bits 47-44 > > > > ID_AA64MMFR2_EL1.AT: bits 35-32 > > > > ID_AA64ISAR0_EL1.RNDR: bits 63-60 > > > > ID_AA64ISAR1_EL1.FRINTTS: bits 35-32 > > ID_AA64ISAR1_EL1.BF16: bits 47-44 > > ID_AA64ISAR1_EL1.DGH: bits 51-48 > > ID_AA64ISAR1_EL1.I8MM: bits 55-52 > > > > ID_AA64ISAR2_EL1.WFxT: bits 3-0 > > ID_AA64ISAR2_EL1.RPRES: bits 7-4 > > ID_AA64ISAR2_EL1.GPA3: bits 11-8 > > ID_AA64ISAR2_EL1.APA3: bits 15-12 > > > > Signed-off-by: Zhuojia Shen <chaosdefinit...@hotmail.com> > > --- > > target/arm/helper.c | 19 ++++++++++++++----- > > 1 file changed, 14 insertions(+), 5 deletions(-) > > > > diff --git a/target/arm/helper.c b/target/arm/helper.c > > index d8c8223ec3..ce6fd7a96d 100644 > > --- a/target/arm/helper.c > > +++ b/target/arm/helper.c > > @@ -7826,13 +7826,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) > > .exported_bits = 0x000f000f00ff0000, > > .fixed_bits = 0x0000000000000011 }, > > { .name = "ID_AA64PFR1_EL1", > > - .exported_bits = 0x00000000000000f0 }, > > + .exported_bits = 0x000000000f000fff }, > > Existing, but I think it would be nicer to do this symbolically. e.g. > > .exported_bits = R_ID_AA64PFR1_BT_MASK | > R_ID_AA64PFR1_SBSS_MASK | > R_ID_AA64PFR1_MTE_MASK | > R_ID_AA64PFR1_SME_MASK, > > etc.
It would be more readable but longer. I can try to refactor this way. > > > r~