On Thu, Dec 08, 2022 at 01:26:42PM +0100, Klaus Jensen wrote:
> From: Klaus Jensen <k.jen...@samsung.com>
>
> Prior to reading the shadow doorbell cq head, we have to update the
> eventidx. Otherwise, we risk that the driver will skip an mmio doorbell
> write. This happens on riscv64, as reported by Guenter.
>
> Adding the missing update to the cq eventidx fixes the issue.
>
> Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support")
> Cc: qemu-sta...@nongnu.org
> Cc: qemu-ri...@nongnu.org
> Reported-by: Guenter Roeck <li...@roeck-us.net>
> Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
Tested-by: Guenter Roeck <li...@roeck-us.net>
> ---
> hw/nvme/ctrl.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
> index cfab21b3436e..f6cc766aba4a 100644
> --- a/hw/nvme/ctrl.c
> +++ b/hw/nvme/ctrl.c
> @@ -1334,6 +1334,14 @@ static inline void nvme_blk_write(BlockBackend *blk,
> int64_t offset,
> }
> }
>
> +static void nvme_update_cq_eventidx(const NvmeCQueue *cq)
> +{
> + trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head);
> +
> + pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &cq->head,
> + sizeof(cq->head));
> +}
> +
> static void nvme_update_cq_head(NvmeCQueue *cq)
> {
> pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head,
> @@ -1355,6 +1363,7 @@ static void nvme_post_cqes(void *opaque)
> hwaddr addr;
>
> if (n->dbbuf_enabled) {
> + nvme_update_cq_eventidx(cq);
> nvme_update_cq_head(cq);
> }
>
