From: Claudio Fontana <cfont...@suse.de> for "all" builds (tcg + kvm), we want to avoid doing the psci and semihosting checks if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana <cfont...@suse.de> Signed-off-by: Fabiano Rosas <faro...@suse.de> --- Originally from: [RFC v14 39/80] target/arm: replace CONFIG_TCG with tcg_enabled https://lore.kernel.org/r/20210416162824.25131-40-cfont...@suse.de --- target/arm/helper.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 45bf164a07..9d0a53cb00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -26,6 +26,7 @@ #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "qemu/range.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" @@ -10300,23 +10301,25 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } - if (arm_is_psci_call(cpu, cs->exception_index)) { - arm_handle_psci_call(cpu); - qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); - return; - } + if (tcg_enabled()) { + if (arm_is_psci_call(cpu, cs->exception_index)) { + arm_handle_psci_call(cpu); + qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + return; + } - /* - * Semihosting semantics depend on the register width of the code - * that caused the exception, not the target exception level, so - * must be handled here. - */ + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. + */ #ifdef CONFIG_TCG - if (cs->exception_index == EXCP_SEMIHOST) { - tcg_handle_semihosting(cs); - return; - } + if (cs->exception_index == EXCP_SEMIHOST) { + tcg_handle_semihosting(cs); + return; + } #endif + } /* Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of -- 2.35.3