On Sat, 17 Dec 2022 at 01:49, Zhuojia Shen <chaosdefinit...@hotmail.com> wrote: > > In CPUID registers exposed to userspace, some registers were missing > and some fields were not exposed. This patch aligns exposed ID > registers and their fields with what the upstream kernel currently > exposes.
This fails to compile the test program on my system: /tmp/ccWsT6Ea.s: Assembler messages: /tmp/ccWsT6Ea.s:413: Error: unknown or missing system register name at operand 2 -- `mrs x0,id_aa64isar2_el1' /tmp/ccWsT6Ea.s:544: Error: selected processor does not support system register name 'id_aa64mmfr2_el1' because the assembler is too old to recognize these newer ID register names. I'm going to fix this by squashing in this change, which uses the fallback Sn_n_Cn_Cn_n syntax instead: diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c index 7d9b0168da2..46b931f781d 100644 --- a/tests/tcg/aarch64/sysregs.c +++ b/tests/tcg/aarch64/sysregs.c @@ -22,6 +22,13 @@ #define HWCAP_CPUID (1 << 11) #endif +/* + * Older assemblers don't recognize newer system register names, + * but we can still access them by the Sn_n_Cn_Cn_n syntax. + */ +#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2 +#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + int failed_bit_count; /* Read and print system register `id' value */ @@ -114,11 +121,11 @@ int main(void) */ get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0)); get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff)); - get_cpu_reg_check_mask(id_aa64isar2_el1, _m(0000,0000,0000,ffff)); + get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff)); /* TGran4 & TGran64 as pegged to -1 */ get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000)); get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000)); - get_cpu_reg_check_mask(id_aa64mmfr2_el1, _m(0000,000f,0000,0000)); + get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000)); /* EL1/EL0 reported as AA64 only */ get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011)); get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0f00,0fff)); Applied to target-arm.next, thanks. -- PMM