On Thu, 5 Jan 2023 at 22:13, Evgeny Iakovlev
<eiakov...@linux.microsoft.com> wrote:
>
> ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
> to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
> uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
> write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is
> enabled and exposed to the guest. As a result EL3 writes of that bit are
> ignored.
>
> Signed-off-by: Evgeny Iakovlev <eiakov...@linux.microsoft.com>
> ---
> target/arm/helper.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index bac2ea62c4..962affdd52 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1844,6 +1844,9 @@ static void scr_write(CPUARMState *env, const
> ARMCPRegInfo *ri, uint64_t value)
> if (cpu_isar_feature(aa64_sme, cpu)) {
> valid_mask |= SCR_ENTP2;
> }
> + if (cpu_isar_feature(aa64_hcx, cpu)) {
> + valid_mask |= SCR_HXEN;
> + }
> } else {
> valid_mask &= ~(SCR_RW | SCR_ST);
> if (cpu_isar_feature(aa32_ras, cpu)) {
> --
Oops. This is worth
Cc: qemu-sta...@nongnu.org
I think.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
I'll take this 3rd patch into target-arm.next now; I've left
review comments for the other 2.
thanks
-- PMM
