On Fri, 20 Jan 2023 at 15:54, Evgeny Iakovlev <eiakov...@linux.microsoft.com> wrote: > > PL011 can be in either of 2 modes depending guest config: FIFO and > single register. The last mode could be viewed as a 1-element-deep FIFO. > > Current code open-codes a bunch of depth-dependent logic. Refactor FIFO > depth handling code to isolate calculating current FIFO depth. > > One functional (albeit guest-invisible) side-effect of this change is > that previously we would always increment s->read_pos in UARTDR read > handler even if FIFO was disabled, now we are limiting read_pos to not > exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO). > > Signed-off-by: Evgeny Iakovlev <eiakov...@linux.microsoft.com> > ---
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
