On Mon, Jan 30, 2023 at 5:29 AM Bin Meng <bmeng...@gmail.com> wrote:
>
> On Thu, Jan 26, 2023 at 12:24 AM Alexandre Ghiti <alexgh...@rivosinc.com>
> wrote:
> >
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
>
> nits: s/qemu/QEMU/g
Ok
>
> >
> > But we actually need to add another level of constraint: what the hw is
> > actually capable of, because currently, a linux booting on a sifive-u54
> > boots in sv57 mode which is incompatible with the cpu's sv39 max
> > capability.
> >
> > So add a new bitmap to RISCVSATPMap which contains this capability and
> > initialize it in every XXX_cpu_init.
> >
> > Finally:
> > - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use
> > - the CPU hw capabilities constrains what the user may select
> > - the user's selection then constrains what's available to the guest
> > OS.
> >
> > Signed-off-by: Alexandre Ghiti <alexgh...@rivosinc.com>
> > Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
> > ---
> > target/riscv/cpu.c | 74 +++++++++++++++++++++++++++++++---------------
> > target/riscv/cpu.h | 8 +++--
> > 2 files changed, 56 insertions(+), 26 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 54494a72be..e7e1fb96dc 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool
> > is_32_bit)
> > g_assert_not_reached();
> > }
> >
> > -/* Sets the satp mode to the max supported */
> > -static void set_satp_mode_default(RISCVCPU *cpu)
> > +static void set_satp_mode_max_supported(RISCVCPU *cpu,
> > + uint8_t satp_mode)
> > {
> > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
> > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
> >
> > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) {
> > - cpu->cfg.satp_mode.map |=
> > - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57"));
> > - } else {
> > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare"));
> > + for (int i = 0; i <= satp_mode; ++i) {
> > + if (valid_vm[i]) {
> > + cpu->cfg.satp_mode.supported |= (1 << i);
> > + }
> > }
> > }
> >
> > +/* Sets the satp mode to the max supported */
>
> nits: s/Sets/Set
Ok
>
> > +static void set_satp_mode_default(RISCVCPU *cpu)
> > +{
> > + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
> > +}
> > +
> > static void riscv_any_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > + RISCVCPU *cpu = RISCV_CPU(obj);
> > +
> > #if defined(TARGET_RISCV32)
> > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> > + set_satp_mode_max_supported(cpu, VM_1_10_SV32);
> > #elif defined(TARGET_RISCV64)
> > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> > + set_satp_mode_max_supported(cpu, VM_1_10_SV57);
> > #endif
> > set_priv_version(env, PRIV_VERSION_1_12_0);
> > register_cpu_props(obj);
> > @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj)
> > static void rv64_base_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > + RISCVCPU *cpu = RISCV_CPU(obj);
> > +
> > /* We set this in the realise function */
> > set_misa(env, MXL_RV64, 0);
> > register_cpu_props(obj);
> > /* Set latest version of privileged specification */
> > set_priv_version(env, PRIV_VERSION_1_12_0);
> > + set_satp_mode_max_supported(cpu, VM_1_10_SV57);
> > }
> >
> > static void rv64_sifive_u_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > + RISCVCPU *cpu = RISCV_CPU(obj);
> > +
> > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > set_priv_version(env, PRIV_VERSION_1_10_0);
> > + set_satp_mode_max_supported(cpu, VM_1_10_SV39);
> > }
> >
> > static void rv64_sifive_e_cpu_init(Object *obj)
> > @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
> > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> > set_priv_version(env, PRIV_VERSION_1_10_0);
> > cpu->cfg.mmu = false;
> > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> > }
> >
> > static void rv128_base_cpu_init(Object *obj)
> > @@ -354,11 +371,13 @@ static void rv128_base_cpu_init(Object *obj)
> > exit(EXIT_FAILURE);
> > }
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > + RISCVCPU *cpu = RISCV_CPU(obj);
> > /* We set this in the realise function */
> > set_misa(env, MXL_RV128, 0);
> > register_cpu_props(obj);
> > /* Set latest version of privileged specification */
> > set_priv_version(env, PRIV_VERSION_1_12_0);
> > + set_satp_mode_max_supported(cpu, VM_1_10_SV57);
> > }
> > #else
> > static void rv32_base_cpu_init(Object *obj)
> > @@ -369,13 +388,17 @@ static void rv32_base_cpu_init(Object *obj)
> > register_cpu_props(obj);
> > /* Set latest version of privileged specification */
> > set_priv_version(env, PRIV_VERSION_1_12_0);
> > + set_satp_mode_max_supported(cpu, VM_1_10_SV32);
>
> Does this compile? 'cpu' seems undeclared ..?
Oops, thanks.
>
> > }
> >
> > static void rv32_sifive_u_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > + RISCVCPU *cpu = RISCV_CPU(obj);
> > +
> > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > set_priv_version(env, PRIV_VERSION_1_10_0);
> > + set_satp_mode_max_supported(cpu, VM_1_10_SV32);
> > }
> >
> > static void rv32_sifive_e_cpu_init(Object *obj)
> > @@ -386,6 +409,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
> > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> > set_priv_version(env, PRIV_VERSION_1_10_0);
> > cpu->cfg.mmu = false;
> > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> > }
> >
> > static void rv32_ibex_cpu_init(Object *obj)
> > @@ -396,6 +420,7 @@ static void rv32_ibex_cpu_init(Object *obj)
> > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> > set_priv_version(env, PRIV_VERSION_1_11_0);
> > cpu->cfg.mmu = false;
> > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> > cpu->cfg.epmp = true;
> > }
> >
> > @@ -407,6 +432,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> > set_priv_version(env, PRIV_VERSION_1_10_0);
> > cpu->cfg.mmu = false;
> > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> > }
> > #endif
> >
> > @@ -698,8 +724,9 @@ static void riscv_cpu_disas_set_info(CPUState *s,
> > disassemble_info *info)
> > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
> > {
> > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
> > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
> > - uint8_t satp_mode_max;
> > + uint8_t satp_mode_map_max;
> > + uint8_t satp_mode_supported_max =
> > +
> > satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
> >
> > if (cpu->cfg.satp_mode.map == 0) {
> > if (cpu->cfg.satp_mode.init == 0) {
> > @@ -713,9 +740,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu,
> > Error **errp)
> > */
> > for (int i = 1; i < 16; ++i) {
> > if ((cpu->cfg.satp_mode.init & (1 << i)) &&
> > - valid_vm[i]) {
> > + (cpu->cfg.satp_mode.supported & (1 << i))) {
> > for (int j = i - 1; j >= 0; --j) {
> > - if (valid_vm[j]) {
> > + if (cpu->cfg.satp_mode.supported & (1 << j)) {
> > cpu->cfg.satp_mode.map |= (1 << j);
> > break;
> > }
> > @@ -726,36 +753,35 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU
> > *cpu, Error **errp)
> > }
> > }
> >
> > - /* Make sure the configuration asked is supported by qemu */
> > - for (int i = 0; i < 16; ++i) {
> > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) {
> > - error_setg(errp, "satp_mode %s is not valid",
> > - satp_mode_str(i, rv32));
> > - return;
> > - }
> > + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> > +
> > + /* Make sure the user asked for a supported configuration (HW and
> > qemu) */
> > + if (satp_mode_map_max > satp_mode_supported_max) {
> > + error_setg(errp, "satp_mode %s is higher than hw max capability
> > %s",
> > + satp_mode_str(satp_mode_map_max, rv32),
> > + satp_mode_str(satp_mode_supported_max, rv32));
> > + return;
> > }
> >
> > /*
> > * Make sure the user did not ask for an invalid configuration as per
> > * the specification.
> > */
> > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> > -
> > if (!rv32) {
> > - for (int i = satp_mode_max - 1; i >= 0; --i) {
> > + for (int i = satp_mode_map_max - 1; i >= 0; --i) {
> > if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
> > (cpu->cfg.satp_mode.init & (1 << i)) &&
> > - valid_vm[i]) {
> > + (cpu->cfg.satp_mode.supported & (1 << i))) {
> > error_setg(errp, "cannot disable %s satp mode if %s "
> > "is enabled", satp_mode_str(i, false),
> > - satp_mode_str(satp_mode_max, false));
> > + satp_mode_str(satp_mode_map_max, false));
> > return;
> > }
> > }
> > }
> >
> > /* Finally expand the map so that all valid modes are set */
> > - for (int i = satp_mode_max - 1; i >= 0; --i) {
> > + for (int i = satp_mode_map_max - 1; i >= 0; --i) {
> > cpu->cfg.satp_mode.map |= (1 << i);
> > }
> > }
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index e37177db5c..b591122099 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -416,13 +416,17 @@ struct RISCVCPUClass {
> >
> > /*
> > * map is a 16-bit bitmap: the most significant set bit in map is the
> > maximum
> > - * satp mode that is supported.
> > + * satp mode that is supported. It may be chosen by the user and must
> > respect
> > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of
> > + * (supported bitmap below).
> > *
> > * init is a 16-bit bitmap used to make sure the user selected a correct
> > * configuration as per the specification.
> > + *
> > + * supported is a 16-bit bitmap used to reflect the hw capabilities.
> > */
> > typedef struct {
> > - uint16_t map, init;
> > + uint16_t map, init, supported;
> > } RISCVSATPMap;
> >
> > struct RISCVCPUConfig {
> > --
>
> Regards,
> Bin
Thanks again,
Alex
