Hi,
In this version we gave up removing all the write_misa() body and,
instead, we went back to something closer to what we were doing in v2.
write_misa() is now gated behind an experimental x-misa-w cfg option,
defaulted to false.
The idea is that x-misa-w allow us to keep experimenting and testing the
code. Marking it as experimental will (hopefully) make users wary of the
fact that this feature is unstable. The expectation is that the flag will
be removed once write_misa() is ready to always write MISA.
Changes from v6:
- patches without reviews/acks: patch 3
- patch 2: taken from version 3, acks and r-bs preserved
- patch 3:
- rename 'misa-w' to 'x-misa-w' to be clearer about our intents with
the cfg option
- v6 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05047.html
Daniel Henrique Barboza (10):
target/riscv: introduce riscv_cpu_cfg()
target/riscv: do not mask unsupported QEMU extensions in write_misa()
target/riscv: allow MISA writes as experimental
target/riscv: remove RISCV_FEATURE_DEBUG
target/riscv/cpu.c: error out if EPMP is enabled without PMP
target/riscv: remove RISCV_FEATURE_EPMP
target/riscv: remove RISCV_FEATURE_PMP
hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in
create_fdt_socket_cpus()
target/riscv: remove RISCV_FEATURE_MMU
target/riscv/cpu: remove CPUArchState::features and friends
hw/riscv/virt.c | 7 ++++---
target/riscv/cpu.c | 25 ++++++++++---------------
target/riscv/cpu.h | 29 ++++++-----------------------
target/riscv/cpu_helper.c | 6 +++---
target/riscv/csr.c | 15 ++++++---------
target/riscv/machine.c | 11 ++++-------
target/riscv/monitor.c | 2 +-
target/riscv/op_helper.c | 2 +-
target/riscv/pmp.c | 8 ++++----
9 files changed, 39 insertions(+), 66 deletions(-)
--
2.39.2
