On Thu, 16 Feb 2023 at 03:10, Richard Henderson <richard.hender...@linaro.org> wrote: > > Pass the individual memop to gen_mte_checkN. > For the moment, do nothing with it. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/arm/translate-a64.h | 2 +- > target/arm/translate-a64.c | 26 +++++++++++++++----------- > target/arm/translate-sve.c | 4 ++-- > 3 files changed, 18 insertions(+), 14 deletions(-) > > diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h > index 3fc39763d0..b7518f9d34 100644 > --- a/target/arm/translate-a64.h > +++ b/target/arm/translate-a64.h > @@ -54,7 +54,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); > TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, > bool tag_checked, MemOp memop); > TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, > - bool tag_checked, int size); > + bool tag_checked, int size, MemOp memop); > > /* We should have at some point before trying to access an FP register > * done the necessary access check, so assert that > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index e02bdd3e7c..1117a1cc41 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -288,7 +288,7 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, > bool is_write, > * For MTE, check multiple logical sequential accesses. > */ > TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, > - bool tag_checked, int size) > + bool tag_checked, int total_size, MemOp single_mop)
Argument name in function definition should match the one in the prototype. Otherwise Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
