W dniu 6.03.2023 o 18:13, Marcin Juszkiewicz pisze:
W dniu 6.03.2023 o 16:37, Peter Maydell pisze:
> On Mon, 6 Mar 2023 at 15:12, Chen Baozi <chenba...@phytium.com.cn>
wrote:
>>
>> Add implementation defined registers for neoverse-n1 which
>> would be accessed by TF-A. Since there is no DSU in Qemu,
>> CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
>>
>> Signed-off-by: Chen Baozi <chenba...@phytium.com.cn>
>> Tested-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
>
> Did Marcin test this version of the patch ?
Hard to test it without updating TF-A first to not use DSU. Older TF-A
starts and then hangs.
Waiting for Chen to provide patch to TF-A and will test.
Tested-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
Adding neoverse_n_common.S turned out to be enough:
~ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 125.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x4
CPU part : 0xd0c
CPU revision : 1
