v3 -> v4: * seperate priv from mmu_idx * use index 2 for S+SUM mmu_idx * no tlb_flush for MPRV / MPP changes
Fei Wu (2): target/riscv: separate priv from mmu_idx target/riscv: reduce overhead of MSTATUS_SUM change target/riscv/cpu.h | 2 -- target/riscv/cpu_helper.c | 19 ++++++++++++++++--- target/riscv/csr.c | 3 +-- .../riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rvh.c.inc | 4 ++-- target/riscv/insn_trans/trans_xthead.c.inc | 7 +------ target/riscv/internals.h | 14 ++++++++++++++ target/riscv/op_helper.c | 5 +++-- target/riscv/translate.c | 3 +++ 9 files changed, 41 insertions(+), 18 deletions(-) -- 2.25.1
