On 2023/3/25 18:54, Richard Henderson wrote:
This builds on Fei and Zhiwei's SUM and TB_FLAGS changes.* Reclaim 5 TB_FLAGS bits, since we nearly ran out. * Using cpu_mmu_index(env, true) is insufficient to implement HLVX properly. While that chooses the correct mmu_idx, it does not perform the read with execute permission. I add a new tcg interface to perform a read-for-execute with an arbitrary mmu_idx. This is still not 100% compliant, but it's closer. * Handle mstatus.MPV in cpu_mmu_index. * Use vsstatus.SUM when required for MMUIdx_S_SUM. * Cleanups for get_physical_address. While this passes check-avocado, I'm sure that's insufficient. Please have a close look. r~ Fei Wu (2): target/riscv: Separate priv from mmu_idx target/riscv: Reduce overhead of MSTATUS_SUM change LIU Zhiwei (4): target/riscv: Extract virt enabled state from tb flags target/riscv: Add a general status enum for extensions target/riscv: Encode the FS and VS on a normal way for tb flags target/riscv: Add a tb flags field for vstart Richard Henderson (19): target/riscv: Remove mstatus_hs_{fs,vs} from tb_flags accel/tcg: Add cpu_ld*_code_mmu target/riscv: Use cpu_ld*_code_mmu for HLVX target/riscv: Handle HLV, HSV via helpers target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT target/riscv: Introduce mmuidx_sum target/riscv: Introduce mmuidx_priv target/riscv: Introduce mmuidx_2stage target/riscv: Move hstatus.spvp check to check_access_hlsv target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index target/riscv: Check SUM in the correct register target/riscv: Hoist second stage mode change to callers target/riscv: Hoist pbmte and hade out of the level loop target/riscv: Move leaf pte processing out of level loop target/riscv: Suppress pte update with is_debug target/riscv: Don't modify SUM with is_debug target/riscv: Merge checks for reserved pte flags target/riscv: Reorg access check in get_physical_address target/riscv: Reorg sum check in get_physical_address include/exec/cpu_ldst.h | 9 + target/riscv/cpu.h | 47 ++- target/riscv/cpu_bits.h | 12 +- target/riscv/helper.h | 12 +- target/riscv/internals.h | 35 ++ accel/tcg/cputlb.c | 48 +++ accel/tcg/user-exec.c | 58 +++ target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 393 +++++++++--------- target/riscv/csr.c | 21 +- target/riscv/op_helper.c | 113 ++++- target/riscv/translate.c | 72 ++-- .../riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rvf.c.inc | 2 +- target/riscv/insn_trans/trans_rvh.c.inc | 135 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 22 +- target/riscv/insn_trans/trans_xthead.c.inc | 7 +- 17 files changed, 595 insertions(+), 395 deletions(-)
This patchset is LGTM. Patch 16 seems fix a bug in the two_stage parameter of raise_mmu_exception
called when translation fails, it didn't take MPV into consideration in original implementation.
Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn> Weiwei Li
