This patch includes:
- VFRSTP[I].{B/H}.
Signed-off-by: Song Gao <gaos...@loongson.cn>
---
target/loongarch/disas.c | 5 +++
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 5 +++
target/loongarch/insns.decode | 5 +++
target/loongarch/lsx_helper.c | 41 +++++++++++++++++++++
5 files changed, 61 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 48c7ea47a4..be2bb9cc42 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1297,3 +1297,8 @@ INSN_LSX(vbitrevi_b, vv_i)
INSN_LSX(vbitrevi_h, vv_i)
INSN_LSX(vbitrevi_w, vv_i)
INSN_LSX(vbitrevi_d, vv_i)
+
+INSN_LSX(vfrstp_b, vvv)
+INSN_LSX(vfrstp_h, vvv)
+INSN_LSX(vfrstpi_b, vv_i)
+INSN_LSX(vfrstpi_h, vv_i)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 4622f788ee..d8b783ebc7 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -525,3 +525,8 @@ DEF_HELPER_4(vbitrevi_b, void, env, i32, i32, i32)
DEF_HELPER_4(vbitrevi_h, void, env, i32, i32, i32)
DEF_HELPER_4(vbitrevi_w, void, env, i32, i32, i32)
DEF_HELPER_4(vbitrevi_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(vfrstp_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vfrstp_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vfrstpi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vfrstpi_h, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 6d3a804767..9ba9113ca3 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -2824,3 +2824,8 @@ TRANS(vbitrevi_b, gen_vv_i, gen_helper_vbitrevi_b)
TRANS(vbitrevi_h, gen_vv_i, gen_helper_vbitrevi_h)
TRANS(vbitrevi_w, gen_vv_i, gen_helper_vbitrevi_w)
TRANS(vbitrevi_d, gen_vv_i, gen_helper_vbitrevi_d)
+
+TRANS(vfrstp_b, gen_vvv, gen_helper_vfrstp_b)
+TRANS(vfrstp_h, gen_vvv, gen_helper_vfrstp_h)
+TRANS(vfrstpi_b, gen_vv_i, gen_helper_vfrstpi_b)
+TRANS(vfrstpi_h, gen_vv_i, gen_helper_vfrstpi_h)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 801c97714e..4cb286ffe5 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -998,3 +998,8 @@ vbitrevi_b 0111 00110001 10000 01 ... ..... .....
@vv_ui3
vbitrevi_h 0111 00110001 10000 1 .... ..... ..... @vv_ui4
vbitrevi_w 0111 00110001 10001 ..... ..... ..... @vv_ui5
vbitrevi_d 0111 00110001 1001 ...... ..... ..... @vv_ui6
+
+vfrstp_b 0111 00010010 10110 ..... ..... ..... @vvv
+vfrstp_h 0111 00010010 10111 ..... ..... ..... @vvv
+vfrstpi_b 0111 00101001 10100 ..... ..... ..... @vv_ui5
+vfrstpi_h 0111 00101001 10101 ..... ..... ..... @vv_ui5
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index e23c75bd56..d6143a0016 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -2288,3 +2288,44 @@ DO_BITI(vbitrevi_b, 8, uint8_t, B, DO_BITREV)
DO_BITI(vbitrevi_h, 16, uint16_t, H, DO_BITREV)
DO_BITI(vbitrevi_w, 32, uint32_t, W, DO_BITREV)
DO_BITI(vbitrevi_d, 64, uint64_t, D, DO_BITREV)
+
+#define VFRSTP(NAME, BIT, MASK, E) \
+void HELPER(NAME)(CPULoongArchState *env, \
+ uint32_t vd, uint32_t vj, uint32_t vk) \
+{ \
+ int i, m; \
+ VReg *Vd = &(env->fpr[vd].vreg); \
+ VReg *Vj = &(env->fpr[vj].vreg); \
+ VReg *Vk = &(env->fpr[vk].vreg); \
+ \
+ for (i = 0; i < LSX_LEN/BIT; i++) { \
+ if (Vj->E(i) < 0) { \
+ break; \
+ } \
+ } \
+ m = Vk->E(0) & MASK; \
+ Vd->E(m) = i; \
+}
+
+VFRSTP(vfrstp_b, 8, 0xf, B)
+VFRSTP(vfrstp_h, 16, 0x7, H)
+
+#define VFRSTPI(NAME, BIT, E) \
+void HELPER(NAME)(CPULoongArchState *env, \
+ uint32_t vd, uint32_t vj, uint32_t imm) \
+{ \
+ int i, m; \
+ VReg *Vd = &(env->fpr[vd].vreg); \
+ VReg *Vj = &(env->fpr[vj].vreg); \
+ \
+ for (i = 0; i < LSX_LEN/BIT; i++) { \
+ if (Vj->E(i) < 0) { \
+ break; \
+ } \
+ } \
+ m = imm % (LSX_LEN/BIT); \
+ Vd->E(m) = i; \
+}
+
+VFRSTPI(vfrstpi_b, 8, B)
+VFRSTPI(vfrstpi_h, 16, H)
--
2.31.1
