On Fri, 31 Mar 2023 at 11:09, Edgar E. Iglesias <edgar.igles...@gmail.com> wrote: > > > On Thu, Mar 23, 2023 at 7:29 PM Chris Rauer <cra...@google.com> wrote: >> >> The problem is that the Linux driver expects the master transaction inhibit >> bit(R_SPICR_MTI) to be set during driver initialization so that it can >> detect the fifo size but QEMU defaults it to zero out of reset. The >> datasheet indicates this bit is active on reset. >> >> See page 25, SPI Control Register section: >> https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf >> > > Yes, MTI should be set when the device comes out of reset. > > Reviewed-by: Edgar E. Iglesias <ed...@zeroasic.com>
Thanks; applied to target-arm.next for 8.0. -- PMM
