On Tue, 18 Apr 2023 at 17:55, Guenter Roeck <li...@roeck-us.net> wrote: > On 4/18/23 08:32, Peter Maydell wrote: > > So looking again at that diagram on that website, I think I understand > > now: for data transfer to/from the outside world, MAC1 talks only through > > PHY1 and MAC2 only through PHY2 (over the links marked "MII/GMII/XGMII"), > > but the "control" connection is via MDIO, and on these boards you have to > > configure PHY2 by doing the MDIO reads and writes via MAC1, even though > > MAC1 has nothing otherwise to do with PHY2 ? (And MAC2 has no devices on > > its MDIO bus at all.) > > > > Correct.
Thanks. Now that I understand how the hardware is put together, I had a think about what the theoretically 'correct' design would be. We could do it, but it's a bit of a pain -- among other things, QEMU's architecture doesn't really consider the idea of devices that are on more than one bus (as the PHY is on both the MDIO and the MII), so you have to pick one as the 'real' bus and then use property links or similar for the other. And we get into having to look at all the other uses of PHYs in QEMU so we can design the interface to be general enough to be usable elsewhere. All of which is more effort than seems worthwhile for just these imx devices. So I'm going to take this series into target-arm.next; if anybody in future wants to properly model the MAC-PHY interface we can feed this use-case in as one of the requirement then... -- PMM
